2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <arch/ioapic.h>
23 #include <device/pci.h>
26 #if CONFIG_LOGICAL_CPUS==1
27 #include <cpu/amd/multicore.h>
29 #include <cpu/amd/amdfam10_sysconf.h>
30 #include "mb_sysconf.h"
32 static void *smp_write_config_table(void *v)
35 struct mp_config_table *mc;
36 struct mb_sysconf_t *m;
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
40 mptable_init(mc, "SERENGETI ", LAPIC_ADDR);
42 smp_write_processors(mc);
49 /* define bus and isa numbers */
50 for(j= 0; j < 256 ; j++) {
52 smp_write_bus(mc, j, "PCI ");
54 smp_write_bus(mc, m->bus_isa, "ISA ");
56 /*I/O APICs: APIC ID Version State Address*/
57 smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
61 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
63 res = find_resource(dev, PCI_BASE_ADDRESS_0);
65 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
68 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
70 res = find_resource(dev, PCI_BASE_ADDRESS_0);
72 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
78 for(i=1; i< sysconf.hc_possible_num; i++) {
79 if(!(sysconf.pci1234[i] & 0x1) ) continue;
81 switch(sysconf.hcid[i]) {
84 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
86 res = find_resource(dev, PCI_BASE_ADDRESS_0);
88 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
91 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
93 res = find_resource(dev, PCI_BASE_ADDRESS_0);
95 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
105 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
107 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
126 // Slot 1 PCI-X 133/100/66
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
132 //Slot 2 PCI-X 133/100/66
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
139 for(i=1; i< sysconf.hc_possible_num; i++) {
140 if(!(sysconf.pci1234[i] & 0x1) ) continue;
144 struct resource *res;
145 switch(sysconf.hcid[i]) {
148 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
150 res = find_resource(dev, PCI_BASE_ADDRESS_0);
152 for(jj=0; jj<4; jj++) {
153 //Slot 1 PCI-X 133/100/66
154 for(ii=0;ii<4;ii++) {
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
161 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
163 res = find_resource(dev, PCI_BASE_ADDRESS_0);
165 for(jj=0; jj<4; jj++) {
166 //Slot 2 PCI-X 133/100/66
167 for(ii=0;ii<4;ii++) {
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
187 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
188 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
189 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
190 /* There is no extension information... */
192 /* Compute the checksums */
193 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
194 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
195 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
196 mc, smp_next_mpe_entry(mc));
197 return smp_next_mpe_entry(mc);
200 unsigned long write_smp_table(unsigned long addr)
203 v = smp_write_floating_table(addr);
204 return (unsigned long)smp_write_config_table(v);