2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <arch/ioapic.h>
23 #include <device/pci.h>
26 #if CONFIG_LOGICAL_CPUS==1
27 #include <cpu/amd/multicore.h>
29 #include <cpu/amd/amdfam10_sysconf.h>
30 #include "mb_sysconf.h"
32 static void *smp_write_config_table(void *v)
35 struct mp_config_table *mc;
36 struct mb_sysconf_t *m;
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
40 mptable_init(mc, LAPIC_ADDR);
42 smp_write_processors(mc);
48 mptable_write_buses(mc, NULL, &bus_isa);
50 /*I/O APICs: APIC ID Version State Address*/
51 smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
55 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
57 res = find_resource(dev, PCI_BASE_ADDRESS_0);
59 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
62 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
64 res = find_resource(dev, PCI_BASE_ADDRESS_0);
66 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
72 for(i=1; i< sysconf.hc_possible_num; i++) {
73 if(!(sysconf.pci1234[i] & 0x1) ) continue;
75 switch(sysconf.hcid[i]) {
78 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
80 res = find_resource(dev, PCI_BASE_ADDRESS_0);
82 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
85 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
87 res = find_resource(dev, PCI_BASE_ADDRESS_0);
89 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
99 mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
101 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
120 // Slot 1 PCI-X 133/100/66
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
126 //Slot 2 PCI-X 133/100/66
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
133 for(i=1; i< sysconf.hc_possible_num; i++) {
134 if(!(sysconf.pci1234[i] & 0x1) ) continue;
138 struct resource *res;
139 switch(sysconf.hcid[i]) {
142 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
144 res = find_resource(dev, PCI_BASE_ADDRESS_0);
146 for(jj=0; jj<4; jj++) {
147 //Slot 1 PCI-X 133/100/66
148 for(ii=0;ii<4;ii++) {
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
155 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
157 res = find_resource(dev, PCI_BASE_ADDRESS_0);
159 for(jj=0; jj<4; jj++) {
160 //Slot 2 PCI-X 133/100/66
161 for(ii=0;ii<4;ii++) {
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
181 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
182 mptable_lintsrc(mc, bus_isa);
183 /* There is no extension information... */
185 /* Compute the checksums */
186 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
187 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
188 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
189 mc, smp_next_mpe_entry(mc));
190 return smp_next_mpe_entry(mc);
193 unsigned long write_smp_table(unsigned long addr)
196 v = smp_write_floating_table(addr, 0);
197 return (unsigned long)smp_write_config_table(v);