2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #define RAMINIT_SYSINFO 1
24 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
26 #define SET_NB_CFG_54 1
29 #define QRANK_DIMM_SUPPORT 1
32 #include <device/pci_def.h>
33 #include <device/pci_ids.h>
35 #include <device/pnp_def.h>
36 #include <arch/romcc_io.h>
37 #include <cpu/x86/lapic.h>
38 #include "option_table.h"
39 #include "pc80/mc146818rtc_early.c"
40 #include "pc80/serial.c"
41 #if CONFIG_USE_INIT == 0
42 #include "lib/memcpy.c"
44 #include "arch/i386/lib/console.c"
46 #include <cpu/amd/model_10xxx_rev.h>
47 #include "northbridge/amd/amdfam10/raminit.h"
48 #include "cpu/amd/model_fxx/apic_timer.c"
50 #include "lib/delay.c"
53 #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn))
55 #define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn)
58 //#include "cpu/x86/lapic/boot_cpu.c"
59 #include "northbridge/amd/amdfam10/reset_test.c"
60 #include "northbridge/amd/amdfam10/debug.c"
61 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
62 #include "northbridge/amd/amdfam10/amdfam10.h"
64 #include "cpu/x86/mtrr.h"
65 #include "cpu/amd/mtrr.h"
66 #include "cpu/x86/tsc.h"
68 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
69 #include "northbridge/amd/amdfam10/amdfam10_conf.c"
70 #include "northbridge/amd/amdfam10/raminit_ddr2_dqs.c"
72 #include "cpu/amd/quadcore/quadcore.c"
74 void hardwaremain(int ret_addr)
76 struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
77 struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
79 struct node_core_id id;
81 id = get_node_core_id_x();
83 printk_debug("CODE IN CACHE ON NODE: %02x\n");
85 train_ram(id.nodeid, sysinfo, sysinfox);
87 /* go back, but can not use stack any more, because we only keep
88 ret_addr and can not restore esp, and ebp */
100 u32 eax, ecx, edx, ebx, esp, ebp, esi, edi;
108 void x86_exception(struct eregs *info)