2 # This file is part of the coreboot project.
4 # Copyright (C) 2007 Advanced Micro Devices, Inc.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; version 2 of the License.
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
15 # You should have received a copy of the GNU General Public License
16 # along with this program; if not, write to the Free Software
17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 uses USE_FALLBACK_IMAGE
25 uses USE_FAILOVER_IMAGE
26 uses HAVE_FALLBACK_BOOT
27 uses HAVE_FAILOVER_BOOT
30 uses HAVE_OPTION_TABLE
32 uses CONFIG_MAX_PHYSICAL_CPUS
33 uses CONFIG_LOGICAL_CPUS
42 uses ROM_SECTION_OFFSET
43 uses CONFIG_ROM_PAYLOAD
44 uses CONFIG_ROM_PAYLOAD_START
45 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
46 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
54 uses LB_CKS_RANGE_START
57 uses MAINBOARD_PART_NUMBER
60 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
61 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
62 uses COREBOOT_EXTRA_VERSION
67 uses DEFAULT_CONSOLE_LOGLEVEL
68 uses MAXIMUM_CONSOLE_LOGLEVEL
69 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
70 uses CONFIG_CONSOLE_SERIAL8250
79 uses CONFIG_CONSOLE_VGA
80 uses CONFIG_PCI_ROM_RUN
81 uses HW_MEM_HOLE_SIZEK
82 uses HW_MEM_HOLE_SIZE_AUTO_INC
84 uses HT_CHAIN_UNITID_BASE
85 uses HT_CHAIN_END_UNITID_BASE
86 uses SB_HT_CHAIN_ON_BUS0
87 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
92 uses DCACHE_RAM_GLOBAL_VAR_SIZE
97 uses ENABLE_APIC_EXT_ID
101 uses CONFIG_PCI_64BIT_PREF_MEM
103 uses CONFIG_LB_MEM_TOPK
105 uses PCI_BUS_SEGN_BITS
107 uses CONFIG_AP_CODE_IN_CAR
111 uses WAIT_BEFORE_CPUS_INIT
115 uses CONFIG_USE_PRINTK_IN_CAR
123 ## ROM_SIZE is the size of boot ROM that this board will use.
125 default ROM_SIZE=524288
129 #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
131 #default FALLBACK_SIZE=131072
132 #default FALLBACK_SIZE=0x40000
135 default FALLBACK_SIZE=0x7f000
137 default FAILOVER_SIZE=0x01000
140 #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
141 default CONFIG_LB_MEM_TOPK=16384
144 ## Build code for the fallback boot
146 default HAVE_FALLBACK_BOOT=1
147 default HAVE_FAILOVER_BOOT=1
150 ## Build code to reset the motherboard from coreboot
152 default HAVE_HARD_RESET=1
155 ## Build code to export a programmable irq routing table
157 default HAVE_PIRQ_TABLE=1
158 default IRQ_SLOT_COUNT=11
161 ## Build code to export an x86 MP table
162 ## Useful for specifying IRQ routing values
164 default HAVE_MP_TABLE=1
166 ## ACPI tables will be included
167 default HAVE_ACPI_TABLES=1
169 default ACPI_SSDTX_NUM=31
172 ## Build code to export a CMOS option table
174 default HAVE_OPTION_TABLE=1
177 ## Move the default coreboot cmos range off of AMD RTC registers
179 default LB_CKS_RANGE_START=49
180 default LB_CKS_RANGE_END=122
181 default LB_CKS_LOC=123
184 ## Build code for SMP support
185 ## Only worry about 2 micro processors
188 default CONFIG_MAX_PHYSICAL_CPUS=2
189 default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
190 default CONFIG_LOGICAL_CPUS=1
192 #default SERIAL_CPU_INIT=0
194 default ENABLE_APIC_EXT_ID=1
195 default APIC_ID_OFFSET=0x00
196 default LIFT_BSP_APIC_ID=1
199 default CONFIG_CHIP_NAME=1
201 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
203 #default HW_MEM_HOLE_SIZEK=0x200000
205 default HW_MEM_HOLE_SIZEK=0x100000
207 #default HW_MEM_HOLE_SIZEK=0x80000
209 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
210 #default HW_MEM_HOLE_SIZE_AUTO_INC=1
213 default CONFIG_CONSOLE_VGA=1
214 default CONFIG_PCI_ROM_RUN=1
216 #HT Unit ID offset, default is 1, the typical one
217 default HT_CHAIN_UNITID_BASE=0xa
219 #real SB Unit ID, default is 0x20, mean dont touch it at last
220 default HT_CHAIN_END_UNITID_BASE=0x6
222 #make the SB HT chain on bus 0, default is not (0)
223 default SB_HT_CHAIN_ON_BUS0=2
225 #only offset for SB chain?, default is yes(1)
226 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
228 #allow capable device use that above 4G
229 #default CONFIG_PCI_64BIT_PREF_MEM=1
231 #it only be 0, 1, 2, 3, 4 and default is 0
232 #default PCI_BUS_SEGN_BITS=3
235 ## enable CACHE_AS_RAM specifics
237 default USE_DCACHE_RAM=1
238 default DCACHE_RAM_BASE=0xc4000
239 default DCACHE_RAM_SIZE=0x0c000
240 #default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
241 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
242 default CONFIG_USE_INIT=0
244 #default CONFIG_AP_CODE_IN_CAR=1
245 default MEM_TRAIN_SEQ=2
246 default WAIT_BEFORE_CPUS_INIT=0
248 default CONFIG_AMDMCT = 1
251 ## Build code to setup a generic IOAPIC
253 default CONFIG_IOAPIC=1
256 ## Clean up the motherboard id strings
258 default MAINBOARD_PART_NUMBER="Cheetah Fam10"
259 default MAINBOARD_VENDOR="AMD"
260 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
261 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
264 ### coreboot layout values
267 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
268 default ROM_IMAGE_SIZE = 65536
271 ## Use a small 8K stack
273 default STACK_SIZE=0x2000
276 ## Use a small 768k heap
278 default HEAP_SIZE=0xc0000
281 ## Only use the option table in a normal image
283 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
286 ## Coreboot C code runs at this location in RAM
288 default _RAMBASE=0x00200000
291 ## Load the payload from the ROM
293 default CONFIG_ROM_PAYLOAD = 1
296 ### Defaults of options that you may want to override in the target config file
300 ## The default compiler
302 default CC="$(CROSS_COMPILE)gcc -m32"
306 ## Disable the gdb stub by default
308 default CONFIG_GDB_STUB=0
311 ## The Serial Console
314 default CONFIG_USE_PRINTK_IN_CAR=1
316 # To Enable the Serial Console
317 default CONFIG_CONSOLE_SERIAL8250=1
319 ## Select the serial console baud rate
320 default TTYS0_BAUD=115200
321 #default TTYS0_BAUD=57600
322 #default TTYS0_BAUD=38400
323 #default TTYS0_BAUD=19200
324 #default TTYS0_BAUD=9600
325 #default TTYS0_BAUD=4800
326 #default TTYS0_BAUD=2400
327 #default TTYS0_BAUD=1200
329 # Select the serial console base port
330 default TTYS0_BASE=0x3f8
332 # Select the serial protocol
333 # This defaults to 8 data bits, 1 stop bit, and no parity
334 default TTYS0_LCS=0x3
337 ### Select the coreboot loglevel
339 ## EMERG 1 system is unusable
340 ## ALERT 2 action must be taken immediately
341 ## CRIT 3 critical conditions
342 ## ERR 4 error conditions
343 ## WARNING 5 warning conditions
344 ## NOTICE 6 normal but significant condition
345 ## INFO 7 informational
346 ## DEBUG 8 debug-level messages
347 ## SPEW 9 Way too many details
349 ## Request this level of debugging output
350 default DEFAULT_CONSOLE_LOGLEVEL=8
351 ## At a maximum only compile in this level of debugging
352 default MAXIMUM_CONSOLE_LOGLEVEL=8
355 ## Select power on after power fail setting
356 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"