remove more warnings. move ROOT_COMPLEX selection to fam10
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_SOCKET_F_1207
5         select NORTHBRIDGE_AMD_AMDFAM10
6         select SOUTHBRIDGE_AMD_AMD8111
7         select SOUTHBRIDGE_AMD_AMD8132
8         select SUPERIO_WINBOND_W83627HF
9         select BOARD_HAS_FADT
10         select HAVE_BUS_CONFIG
11         select HAVE_PIRQ_TABLE
12         select HAVE_MP_TABLE
13         select USE_PRINTK_IN_CAR
14         select USE_DCACHE_RAM
15         select HAVE_HARD_RESET
16         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
17         select SERIAL_CPU_INIT
18         select AMDMCT
19         select HAVE_ACPI_TABLES
20         select BOARD_ROMSIZE_KB_1024
21         select ENABLE_APIC_EXT_ID
22         select LIFT_BSP_APIC_ID
23         select TINY_BOOTBLOCK
24
25 config MAINBOARD_DIR
26         string
27         default amd/serengeti_cheetah_fam10
28         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
29
30 config APIC_ID_OFFSET
31         hex
32         default 0x0
33         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
34
35 config MAINBOARD_PART_NUMBER
36         string
37         default "Serengeti Cheetah (Fam10)"
38         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
39
40 config HW_MEM_HOLE_SIZEK
41         hex
42         default 0x100000
43         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
44
45 # 6 * MAX_PHYSICAL_CPUS
46 config MAX_CPUS
47         int
48         default 48
49         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
50
51 config MAX_PHYSICAL_CPUS
52         int
53         default 8
54         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
55
56 config HW_MEM_HOLE_SIZE_AUTO_INC
57         bool
58         default n
59         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
60
61 config MEM_TRAIN_SEQ
62         int
63         default 2
64         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
65
66 config SB_HT_CHAIN_ON_BUS0
67         int
68         default 2
69         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
70
71 config HT_CHAIN_END_UNITID_BASE
72         hex
73         default 0x6
74         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
75
76 config HT_CHAIN_UNITID_BASE
77         hex
78         default 0xa
79         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
80
81 config IRQ_SLOT_COUNT
82         int
83         default 11
84         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
85
86 config AMD_UCODE_PATCH_FILE
87         string
88         default "mc_patch_01000095.h"
89         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
90
91 config RAMTOP
92         hex
93         default 0x1000000
94         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
95
96 config HEAP_SIZE
97         hex
98         default 0xc0000
99         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
100
101 config ACPI_SSDTX_NUM
102         int
103         default 5
104         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
105
106 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
107         hex
108         default 0x2b80
109         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
110
111 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
112         hex
113         default 0x1022
114         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
115
116 config RAMBASE
117         hex
118         default 0x200000
119         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
120
121 config ID_SECTION_OFFSET
122         hex
123         default 0x80
124         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10