- Add rules that build either 4 or 5 ssdts (only those variants exist in the board...
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_SOCKET_F_1207
5         select NORTHBRIDGE_AMD_AMDFAM10
6         select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
7         select SOUTHBRIDGE_AMD_AMD8111
8         select SOUTHBRIDGE_AMD_AMD8132
9         select SUPERIO_WINBOND_W83627HF
10         select BOARD_HAS_FADT
11         select HAVE_BUS_CONFIG
12         select HAVE_PIRQ_TABLE
13         select HAVE_MP_TABLE
14         select USE_PRINTK_IN_CAR
15         select USE_DCACHE_RAM
16         select HAVE_HARD_RESET
17         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
18         select SERIAL_CPU_INIT
19         select AMDMCT
20         select HAVE_ACPI_TABLES
21         select BOARD_ROMSIZE_KB_1024
22         select ENABLE_APIC_EXT_ID
23         select LIFT_BSP_APIC_ID
24         select TINY_BOOTBLOCK
25
26 config MAINBOARD_DIR
27         string
28         default amd/serengeti_cheetah_fam10
29         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
30
31 config APIC_ID_OFFSET
32         hex
33         default 0x0
34         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
35
36 config LB_CKS_RANGE_END
37         int
38         default 122
39         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
40
41 config LB_CKS_LOC
42         int
43         default 123
44         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
45
46 config MAINBOARD_PART_NUMBER
47         string
48         default "Serengeti Cheetah (Fam10)"
49         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
50
51 config HW_MEM_HOLE_SIZEK
52         hex
53         default 0x100000
54         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
55
56 # 6 * MAX_PHYSICAL_CPUS
57 config MAX_CPUS
58         int
59         default 48
60         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
61
62 config MAX_PHYSICAL_CPUS
63         int
64         default 8
65         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
66
67 config HW_MEM_HOLE_SIZE_AUTO_INC
68         bool
69         default n
70         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
71
72 config MEM_TRAIN_SEQ
73         int
74         default 2
75         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
76
77 config SB_HT_CHAIN_ON_BUS0
78         int
79         default 2
80         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
81
82 config HT_CHAIN_END_UNITID_BASE
83         hex
84         default 0x6
85         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
86
87 config HT_CHAIN_UNITID_BASE
88         hex
89         default 0xa
90         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
91
92 config USE_INIT
93         bool
94         default n
95         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
96
97 config IRQ_SLOT_COUNT
98         int
99         default 11
100         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
101
102 config AMD_UCODE_PATCH_FILE
103         string
104         default "mc_patch_01000095.h"
105         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
106
107 config RAMTOP
108         hex
109         default 0x1000000
110         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
111
112 config HEAP_SIZE
113         hex
114         default 0xc0000
115         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
116
117 config ACPI_SSDTX_NUM
118         int
119         default 5
120         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
121
122 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
123         hex
124         default 0x2b80
125         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
126
127 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
128         hex
129         default 0x1022
130         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
131
132 config RAMBASE
133         hex
134         default 0x200000
135         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
136
137 config ID_SECTION_OFFSET
138         hex
139         default 0x80
140         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10