Add CONFIG_GENERATE_* for tables so that the user can select which tables not
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_FAM10
5         select CPU_AMD_SOCKET_F_1207
6         select NORTHBRIDGE_AMD_AMDFAM10
7         select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
8         select SOUTHBRIDGE_AMD_AMD8111
9         select SOUTHBRIDGE_AMD_AMD8132
10         select SUPERIO_WINBOND_W83627HF
11         select HAVE_PIRQ_TABLE
12         select HAVE_MP_TABLE
13         select USE_PRINTK_IN_CAR
14         select USE_DCACHE_RAM
15         select HAVE_HARD_RESET
16         select IOAPIC
17         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
18         select SERIAL_CPU_INIT
19         select AMDMCT
20         select HAVE_ACPI_TABLES
21
22 config MAINBOARD_DIR
23         string
24         default amd/serengeti_cheetah_fam10
25         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
26
27 config APIC_ID_OFFSET
28         hex
29         default 0x0
30         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
31
32 config LB_CKS_RANGE_END
33         int
34         default 122
35         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
36
37 config LB_CKS_LOC
38         int
39         default 123
40         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
41
42 config MAINBOARD_PART_NUMBER
43         string
44         default "Serengeti-Cheetah-Fam10"
45         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
46
47 config HW_MEM_HOLE_SIZEK
48         hex
49         default 0x100000
50         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
51
52 # 6 * MAX_PHYSICAL_CPUS
53 config MAX_CPUS
54         int
55         default 48
56         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
57
58 config MAX_PHYSICAL_CPUS
59         int
60         default 8
61         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
62
63 config HW_MEM_HOLE_SIZE_AUTO_INC
64         bool
65         default n
66         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
67
68 config SB_HT_CHAIN_ON_BUS0
69         int
70         default 2
71         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
72
73 config HT_CHAIN_END_UNITID_BASE
74         hex
75         default 0x6
76         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
77
78 config HT_CHAIN_UNITID_BASE
79         hex
80         default 0xa
81         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
82
83 config USE_INIT
84         bool
85         default n
86         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
87
88 config IRQ_SLOT_COUNT
89         int
90         default 11
91         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
92
93 config AMD_UCODE_PATCH_FILE
94         string
95         default "mc_patch_01000095.h"
96         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
97
98 config LB_MEM_TOPK
99         hex
100         default 0x4000
101         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
102
103 config HEAP_SIZE
104         hex
105         default 0xc0000
106         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
107
108 config ACPI_SSDTX_NUM
109         int
110         default 31
111         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
112
113 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
114         hex
115         default 0x2b80
116         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
117
118 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
119         hex
120         default 0x1022
121         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
122
123 config ENABLE_APIC_EXT_ID
124         bool
125         default y
126         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
127
128 config LIFT_BSP_APIC_ID
129         bool
130         default y
131         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10