da4ea1faf288a7d673aaad33f4edd2fab8b16f88
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_FAM10
5         select CPU_AMD_SOCKET_F_1207
6         select NORTHBRIDGE_AMD_AMDFAM10
7         select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
8         select SOUTHBRIDGE_AMD_AMD8111
9         select SOUTHBRIDGE_AMD_AMD8132
10         select SUPERIO_WINBOND_W83627HF
11         select HAVE_PIRQ_TABLE
12         select USE_PRINTK_IN_CAR
13         select USE_DCACHE_RAM
14         select HAVE_HARD_RESET
15         select IOAPIC
16         select AP_CODE_IN_CAR
17         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
18         select WAIT_BEFORE_CPUS_INIT
19         select AMDMCT
20         select HAVE_ACPI_TABLES
21
22 config MAINBOARD_DIR
23         string
24         default amd/serengeti_cheetah_fam10
25         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
26
27 config DCACHE_RAM_BASE
28         hex
29         default 0xc8000
30         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
31
32 config DCACHE_RAM_SIZE
33         hex
34         default 0x08000
35         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
36
37 config DCACHE_RAM_GLOBAL_VAR_SIZE
38         hex
39         default 0x01000
40         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
41
42 config APIC_ID_OFFSET
43         hex
44         default 0x8
45         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
46
47 config LB_CKS_RANGE_END
48         int
49         default 122
50         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
51
52 config LB_CKS_LOC
53         int
54         default 123
55         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
56
57 config MAINBOARD_PART_NUMBER
58         string
59         default "Serengeti-Cheetah-Fam10"
60         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
61
62 config HW_MEM_HOLE_SIZEK
63         hex
64         default 0x100000
65         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
66
67 # 6 * MAX_PHYSICAL_CPUS
68 config MAX_CPUS
69         int
70         default 48
71         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
72
73 config MAX_PHYSICAL_CPUS
74         int
75         default 8
76         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
77
78 config HW_MEM_HOLE_SIZE_AUTO_INC
79         bool
80         default n
81         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
82
83 config SB_HT_CHAIN_ON_BUS0
84         int
85         default 2
86         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
87
88 config HT_CHAIN_END_UNITID_BASE
89         hex
90         default 0x6
91         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
92
93 config HT_CHAIN_UNITID_BASE
94         hex
95         default 0xa
96         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
97
98 config USE_INIT
99         bool
100         default n
101         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
102
103 config SERIAL_CPU_INIT
104         bool
105         default n
106         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
107
108 config IRQ_SLOT_COUNT
109         int
110         default 11
111         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
112
113 config AMD_UCODE_PATCH_FILE
114         string
115         default "mc_patch_01000095.h"
116         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
117