Set default ROM sizes per-board to match the ROM chip that came
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_FAM10
5         select CPU_AMD_SOCKET_F_1207
6         select NORTHBRIDGE_AMD_AMDFAM10
7         select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
8         select SOUTHBRIDGE_AMD_AMD8111
9         select SOUTHBRIDGE_AMD_AMD8132
10         select SUPERIO_WINBOND_W83627HF
11         select HAVE_PIRQ_TABLE
12         select HAVE_MP_TABLE
13         select USE_PRINTK_IN_CAR
14         select USE_DCACHE_RAM
15         select HAVE_HARD_RESET
16         select IOAPIC
17         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
18         select SERIAL_CPU_INIT
19         select AMDMCT
20         select HAVE_ACPI_TABLES
21         select BOARD_ROMSIZE_KB_1024
22
23 config MAINBOARD_DIR
24         string
25         default amd/serengeti_cheetah_fam10
26         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
27
28 config APIC_ID_OFFSET
29         hex
30         default 0x0
31         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
32
33 config LB_CKS_RANGE_END
34         int
35         default 122
36         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
37
38 config LB_CKS_LOC
39         int
40         default 123
41         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
42
43 config MAINBOARD_PART_NUMBER
44         string
45         default "Serengeti-Cheetah-Fam10"
46         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
47
48 config HW_MEM_HOLE_SIZEK
49         hex
50         default 0x100000
51         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
52
53 # 6 * MAX_PHYSICAL_CPUS
54 config MAX_CPUS
55         int
56         default 48
57         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
58
59 config MAX_PHYSICAL_CPUS
60         int
61         default 8
62         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
63
64 config HW_MEM_HOLE_SIZE_AUTO_INC
65         bool
66         default n
67         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
68
69 config SB_HT_CHAIN_ON_BUS0
70         int
71         default 2
72         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
73
74 config HT_CHAIN_END_UNITID_BASE
75         hex
76         default 0x6
77         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
78
79 config HT_CHAIN_UNITID_BASE
80         hex
81         default 0xa
82         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
83
84 config USE_INIT
85         bool
86         default n
87         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
88
89 config IRQ_SLOT_COUNT
90         int
91         default 11
92         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
93
94 config AMD_UCODE_PATCH_FILE
95         string
96         default "mc_patch_01000095.h"
97         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
98
99 config RAMTOP
100         hex
101         default 0x1000000
102         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
103
104 config HEAP_SIZE
105         hex
106         default 0xc0000
107         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
108
109 config ACPI_SSDTX_NUM
110         int
111         default 31
112         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
113
114 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
115         hex
116         default 0x2b80
117         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
118
119 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
120         hex
121         default 0x1022
122         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
123
124 config ENABLE_APIC_EXT_ID
125         bool
126         default y
127         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
128
129 config LIFT_BSP_APIC_ID
130         bool
131         default y
132         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10