src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by raminit
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 //used by incoherent_ht
   7 //#define K8_ALLOCATE_IO_RANGE 1
   8
   9 //used by init_cpus and fidvid
  10 #define SET_FIDVID 0
  11 //if we want to wait for core1 done before DQS training, set it to 0
  12 #define SET_FIDVID_CORE0_ONLY 1
  13
  14 #if CONFIG_K8_REV_F_SUPPORT == 1
  15 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  16 #endif
  17
  18 #include <stdint.h>
  19 #include <string.h>
  20 #include <device/pci_def.h>
  21 #include <device/pci_ids.h>
  22 #include <arch/io.h>
  23 #include <device/pnp_def.h>
  24 #include <arch/romcc_io.h>
  25 #include <cpu/x86/lapic.h>
  26 #include <pc80/mc146818rtc.h>
  27
  28 #include <console/console.h>
  29 #include <cpu/amd/model_fxx_rev.h>
  30 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  31 #include <reset.h>
  32 #include "northbridge/amd/amdk8/raminit.h"
  33 #include "cpu/amd/model_fxx/apic_timer.c"
  34
  35 #include "cpu/x86/lapic/boot_cpu.c"
  36 #include "northbridge/amd/amdk8/reset_test.c"
  37
  38 #include "cpu/x86/bist.h"
  39
  40 #include "lib/delay.c"
  41
  42 #include "northbridge/amd/amdk8/debug.c"
  43 #include "cpu/x86/mtrr/earlymtrr.c"
  44 #include <cpu/amd/mtrr.h>
  45 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  46
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48
  49 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  50
  51 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  52
  53 static void memreset_setup(void)
  54 {
  55         //GPIO on amd8111 to enable MEMRST ????
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  57         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  58 }
  59
  60 static void memreset(int controllers, const struct mem_controller *ctrl)
  61 {
  62 }
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66 #define SMBUS_HUB 0x18
  67         int ret,i;
  68         unsigned device=(ctrl->channel0[0])>>8;
  69         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  70         i=2;
  71         do {
  72                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  73         } while ((ret!=0) && (i-->0));
  74
  75         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  76 }
  77 #if 0
  78 static inline void change_i2c_mux(unsigned device)
  79 {
  80 #define SMBUS_HUB 0x18
  81         int ret, i;
  82         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  83         i=2;
  84         do {
  85                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  86                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  87         } while ((ret!=0) && (i-->0));
  88         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  89         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  90 }
  91 #endif
  92
  93 static inline int spd_read_byte(unsigned device, unsigned address)
  94 {
  95         return smbus_read_byte(device, address);
  96 }
  97
  98 #include "northbridge/amd/amdk8/amdk8.h"
  99 #include "northbridge/amd/amdk8/incoherent_ht.c"
 100 #include "northbridge/amd/amdk8/coherent_ht.c"
 101 #include "northbridge/amd/amdk8/raminit_f.c"
 102 #include "lib/generic_sdram.c"
 103
 104  /* tyan does not want the default */
 105 #include "resourcemap.c"
 106
 107 #include "cpu/amd/dualcore/dualcore.c"
 108
 109 #define RC0 ((1<<0)<<8)
 110 #define RC1 ((1<<1)<<8)
 111 #define RC2 ((1<<2)<<8)
 112 #define RC3 ((1<<3)<<8)
 113
 114 #define DIMM0 0x50
 115 #define DIMM1 0x51
 116 #define DIMM2 0x52
 117 #define DIMM3 0x53
 118 #define DIMM4 0x54
 119 #define DIMM5 0x55
 120 #define DIMM6 0x56
 121 #define DIMM7 0x57
 122
 123
 124 #include "cpu/amd/car/post_cache_as_ram.c"
 125
 126 #include "cpu/amd/model_fxx/init_cpus.c"
 127
 128 #include "cpu/amd/model_fxx/fidvid.c"
 129
 130 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 131 #include "northbridge/amd/amdk8/early_ht.c"
 132
 133 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 134 {
 135         static const uint16_t spd_addr[] = {
 136                         //first node
 137                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 138                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 139 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 140                         //second node
 141                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 142                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 143 #endif
 144 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 145                         // third node
 146                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 147                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 148                         // four node
 149                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 150                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 151 #endif
 152
 153         };
 154
 155         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 156
 157         int needs_reset;
 158         unsigned bsp_apicid = 0;
 159 #if SET_FIDVID == 1
 160         struct cpuid_result cpuid1;
 161 #endif
 162
 163         if (!cpu_init_detectedx && boot_cpu()) {
 164                 /* Nothing special needs to be done to find bus 0 */
 165                 /* Allow the HT devices to be found */
 166
 167                 enumerate_ht_chain();
 168
 169                 /* Setup the rom access for 4M */
 170                 amd8111_enable_rom();
 171         }
 172
 173         if (bist == 0) {
 174                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 175         }
 176
 177 //      post_code(0x32);
 178
 179         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 180         uart_init();
 181         console_init();
 182
 183 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 184
 185         /* Halt if there was a built in self test failure */
 186         report_bist_failure(bist);
 187
 188         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 189
 190         setup_mb_resource_map();
 191 #if 0
 192         dump_pci_device(PCI_DEV(0, 0x18, 0));
 193         dump_pci_device(PCI_DEV(0, 0x19, 0));
 194 #endif
 195
 196         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 197
 198 #if CONFIG_MEM_TRAIN_SEQ == 1
 199         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 200 #endif
 201         setup_coherent_ht_domain(); // routing table and start other core0
 202
 203         wait_all_core0_started();
 204 #if CONFIG_LOGICAL_CPUS==1
 205         // It is said that we should start core1 after all core0 launched
 206         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 207          * So here need to make sure last core0 is started, esp for two way system,
 208          * (there may be apic id conflicts in that case)
 209          */
 210         start_other_cores();
 211         wait_all_other_cores_started(bsp_apicid);
 212 #endif
 213
 214         /* it will set up chains and store link pair for optimization later */
 215         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 216
 217 #if 0
 218         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 219         needs_reset = optimize_link_coherent_ht();
 220         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 221 #endif
 222
 223 #if SET_FIDVID == 1
 224         /* Check to see if processor is capable of changing FIDVID  */
 225         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 226         cpuid1 = cpuid(0x80000007);
 227         if( (cpuid1.edx & 0x6) == 0x6 ) {
 228
 229         {
 230                 /* Read FIDVID_STATUS */
 231                 msr_t msr;
 232                 msr=rdmsr(0xc0010042);
 233                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 234
 235         }
 236
 237         enable_fid_change();
 238
 239         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 240
 241         init_fidvid_bsp(bsp_apicid);
 242
 243         // show final fid and vid
 244         {
 245                 msr_t msr;
 246                 msr=rdmsr(0xc0010042);
 247                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 248
 249         }
 250
 251         } else {
 252                 print_debug("Changing FIDVID not supported\n");
 253         }
 254
 255 #endif
 256
 257 #if 1
 258         needs_reset = optimize_link_coherent_ht();
 259         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 260
 261         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 262         if (needs_reset) {
 263                 print_info("ht reset -\n");
 264                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 265         }
 266 #endif
 267         allow_all_aps_stop(bsp_apicid);
 268
 269         //It's the time to set ctrl in sysinfo now;
 270         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 271
 272         enable_smbus();
 273
 274 #if 0
 275         int i;
 276         for(i=0;i<4;i++) {
 277                 activate_spd_rom(&cpu[i]);
 278                 dump_smbus_registers();
 279         }
 280 #endif
 281
 282 #if 0
 283         for(i=1;i<256;i<<=1) {
 284                 change_i2c_mux(i);
 285                 dump_smbus_registers();
 286         }
 287 #endif
 288
 289         memreset_setup();
 290
 291         //do we need apci timer, tsc...., only debug need it for better output
 292         /* all ap stopped? */
 293 //        init_timer(); // Need to use TMICT to synconize FID/VID
 294
 295         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 296
 297 #if 0
 298         print_pci_devices();
 299 #endif
 300
 301 #if 0
 302 //        dump_pci_devices();
 303         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 304         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 305 #endif
 306
 307         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 308
 309 }
 310