src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14
  15 #include <console/console.h>
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include <reset.h>
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24
  25 #include "cpu/x86/bist.h"
  26
  27 #include "lib/delay.c"
  28
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "cpu/x86/mtrr/earlymtrr.c"
  31 #include <cpu/amd/mtrr.h>
  32 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  39
  40 static void memreset_setup(void)
  41 {
  42         //GPIO on amd8111 to enable MEMRST ????
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49 }
  50
  51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  52 {
  53 #define SMBUS_HUB 0x18
  54         int ret,i;
  55         unsigned device=(ctrl->channel0[0])>>8;
  56         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  57         i=2;
  58         do {
  59                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  60         } while ((ret!=0) && (i-->0));
  61
  62         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  63 }
  64 #if 0
  65 static inline void change_i2c_mux(unsigned device)
  66 {
  67 #define SMBUS_HUB 0x18
  68         int ret, i;
  69         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  70         i=2;
  71         do {
  72                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  73                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  74         } while ((ret!=0) && (i-->0));
  75         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  76         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  77 }
  78 #endif
  79
  80 static inline int spd_read_byte(unsigned device, unsigned address)
  81 {
  82         return smbus_read_byte(device, address);
  83 }
  84
  85 #include "northbridge/amd/amdk8/amdk8.h"
  86 #include "northbridge/amd/amdk8/incoherent_ht.c"
  87 #include "northbridge/amd/amdk8/coherent_ht.c"
  88 #include "northbridge/amd/amdk8/raminit_f.c"
  89 #include "lib/generic_sdram.c"
  90
  91  /* tyan does not want the default */
  92 #include "resourcemap.c"
  93
  94 #include "cpu/amd/dualcore/dualcore.c"
  95
  96 #define RC0 ((1<<0)<<8)
  97 #define RC1 ((1<<1)<<8)
  98 #define RC2 ((1<<2)<<8)
  99 #define RC3 ((1<<3)<<8)
 100
 101 #define DIMM0 0x50
 102 #define DIMM1 0x51
 103 #define DIMM2 0x52
 104 #define DIMM3 0x53
 105 #define DIMM4 0x54
 106 #define DIMM5 0x55
 107 #define DIMM6 0x56
 108 #define DIMM7 0x57
 109
 110
 111 #include "cpu/amd/car/post_cache_as_ram.c"
 112
 113 #include "cpu/amd/model_fxx/init_cpus.c"
 114
 115 #include "cpu/amd/model_fxx/fidvid.c"
 116
 117 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 118 #include "northbridge/amd/amdk8/early_ht.c"
 119
 120 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 121 {
 122         static const uint16_t spd_addr[] = {
 123                         //first node
 124                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 125                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 126 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 127                         //second node
 128                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 129                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 130 #endif
 131 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 132                         // third node
 133                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 134                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 135                         // four node
 136                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 137                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 138 #endif
 139
 140         };
 141
 142         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 143
 144         int needs_reset;
 145         unsigned bsp_apicid = 0;
 146 #if CONFIG_SET_FIDVID
 147         struct cpuid_result cpuid1;
 148 #endif
 149
 150         if (!cpu_init_detectedx && boot_cpu()) {
 151                 /* Nothing special needs to be done to find bus 0 */
 152                 /* Allow the HT devices to be found */
 153
 154                 enumerate_ht_chain();
 155
 156                 /* Setup the rom access for 4M */
 157                 amd8111_enable_rom();
 158         }
 159
 160         if (bist == 0) {
 161                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 162         }
 163
 164 //      post_code(0x32);
 165
 166         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 167         uart_init();
 168         console_init();
 169
 170 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 171
 172         /* Halt if there was a built in self test failure */
 173         report_bist_failure(bist);
 174
 175         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 176
 177         setup_mb_resource_map();
 178 #if 0
 179         dump_pci_device(PCI_DEV(0, 0x18, 0));
 180         dump_pci_device(PCI_DEV(0, 0x19, 0));
 181 #endif
 182
 183         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 184
 185 #if CONFIG_MEM_TRAIN_SEQ == 1
 186         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 187 #endif
 188         setup_coherent_ht_domain(); // routing table and start other core0
 189
 190         wait_all_core0_started();
 191 #if CONFIG_LOGICAL_CPUS==1
 192         // It is said that we should start core1 after all core0 launched
 193         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 194          * So here need to make sure last core0 is started, esp for two way system,
 195          * (there may be apic id conflicts in that case)
 196          */
 197         start_other_cores();
 198         wait_all_other_cores_started(bsp_apicid);
 199 #endif
 200
 201         /* it will set up chains and store link pair for optimization later */
 202         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 203
 204 #if 0
 205         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 206         needs_reset = optimize_link_coherent_ht();
 207         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 208 #endif
 209
 210 #if CONFIG_SET_FIDVID
 211         /* Check to see if processor is capable of changing FIDVID  */
 212         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 213         cpuid1 = cpuid(0x80000007);
 214         if( (cpuid1.edx & 0x6) == 0x6 ) {
 215
 216         {
 217                 /* Read FIDVID_STATUS */
 218                 msr_t msr;
 219                 msr=rdmsr(0xc0010042);
 220                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 221
 222         }
 223
 224         enable_fid_change();
 225
 226         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 227
 228         init_fidvid_bsp(bsp_apicid);
 229
 230         // show final fid and vid
 231         {
 232                 msr_t msr;
 233                 msr=rdmsr(0xc0010042);
 234                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 235
 236         }
 237
 238         } else {
 239                 print_debug("Changing FIDVID not supported\n");
 240         }
 241
 242 #endif
 243
 244 #if 1
 245         needs_reset = optimize_link_coherent_ht();
 246         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 247
 248         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 249         if (needs_reset) {
 250                 print_info("ht reset -\n");
 251                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 252         }
 253 #endif
 254         allow_all_aps_stop(bsp_apicid);
 255
 256         //It's the time to set ctrl in sysinfo now;
 257         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 258
 259         enable_smbus();
 260
 261 #if 0
 262         int i;
 263         for(i=0;i<4;i++) {
 264                 activate_spd_rom(&cpu[i]);
 265                 dump_smbus_registers();
 266         }
 267 #endif
 268
 269 #if 0
 270         for(i=1;i<256;i<<=1) {
 271                 change_i2c_mux(i);
 272                 dump_smbus_registers();
 273         }
 274 #endif
 275
 276         memreset_setup();
 277
 278         //do we need apci timer, tsc...., only debug need it for better output
 279         /* all ap stopped? */
 280 //        init_timer(); // Need to use TMICT to synconize FID/VID
 281
 282         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 283
 284 #if 0
 285         print_pci_devices();
 286 #endif
 287
 288 #if 0
 289 //        dump_pci_devices();
 290         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 291         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 292 #endif
 293
 294         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 295
 296 }
 297