src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by init_cpus and fidvid
   4 #define SET_FIDVID 0
   5 //if we want to wait for core1 done before DQS training, set it to 0
   6 #define SET_FIDVID_CORE0_ONLY 1
   7
   8 #if CONFIG_K8_REV_F_SUPPORT == 1
   9 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  10 #endif
  11
  12 #include <stdint.h>
  13 #include <string.h>
  14 #include <device/pci_def.h>
  15 #include <device/pci_ids.h>
  16 #include <arch/io.h>
  17 #include <device/pnp_def.h>
  18 #include <arch/romcc_io.h>
  19 #include <cpu/x86/lapic.h>
  20 #include <pc80/mc146818rtc.h>
  21
  22 #include <console/console.h>
  23 #include <cpu/amd/model_fxx_rev.h>
  24 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  25 #include <reset.h>
  26 #include "northbridge/amd/amdk8/raminit.h"
  27 #include "cpu/amd/model_fxx/apic_timer.c"
  28
  29 #include "cpu/x86/lapic/boot_cpu.c"
  30 #include "northbridge/amd/amdk8/reset_test.c"
  31
  32 #include "cpu/x86/bist.h"
  33
  34 #include "lib/delay.c"
  35
  36 #include "northbridge/amd/amdk8/debug.c"
  37 #include "cpu/x86/mtrr/earlymtrr.c"
  38 #include <cpu/amd/mtrr.h>
  39 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  40
  41 #include "northbridge/amd/amdk8/setup_resource_map.c"
  42
  43 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  44
  45 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  46
  47 static void memreset_setup(void)
  48 {
  49         //GPIO on amd8111 to enable MEMRST ????
  50         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  51         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56 }
  57
  58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  59 {
  60 #define SMBUS_HUB 0x18
  61         int ret,i;
  62         unsigned device=(ctrl->channel0[0])>>8;
  63         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  64         i=2;
  65         do {
  66                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  67         } while ((ret!=0) && (i-->0));
  68
  69         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  70 }
  71 #if 0
  72 static inline void change_i2c_mux(unsigned device)
  73 {
  74 #define SMBUS_HUB 0x18
  75         int ret, i;
  76         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  77         i=2;
  78         do {
  79                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  80                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  81         } while ((ret!=0) && (i-->0));
  82         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  83         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  84 }
  85 #endif
  86
  87 static inline int spd_read_byte(unsigned device, unsigned address)
  88 {
  89         return smbus_read_byte(device, address);
  90 }
  91
  92 #include "northbridge/amd/amdk8/amdk8.h"
  93 #include "northbridge/amd/amdk8/incoherent_ht.c"
  94 #include "northbridge/amd/amdk8/coherent_ht.c"
  95 #include "northbridge/amd/amdk8/raminit_f.c"
  96 #include "lib/generic_sdram.c"
  97
  98  /* tyan does not want the default */
  99 #include "resourcemap.c"
 100
 101 #include "cpu/amd/dualcore/dualcore.c"
 102
 103 #define RC0 ((1<<0)<<8)
 104 #define RC1 ((1<<1)<<8)
 105 #define RC2 ((1<<2)<<8)
 106 #define RC3 ((1<<3)<<8)
 107
 108 #define DIMM0 0x50
 109 #define DIMM1 0x51
 110 #define DIMM2 0x52
 111 #define DIMM3 0x53
 112 #define DIMM4 0x54
 113 #define DIMM5 0x55
 114 #define DIMM6 0x56
 115 #define DIMM7 0x57
 116
 117
 118 #include "cpu/amd/car/post_cache_as_ram.c"
 119
 120 #include "cpu/amd/model_fxx/init_cpus.c"
 121
 122 #include "cpu/amd/model_fxx/fidvid.c"
 123
 124 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 125 #include "northbridge/amd/amdk8/early_ht.c"
 126
 127 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 128 {
 129         static const uint16_t spd_addr[] = {
 130                         //first node
 131                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 132                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 133 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 134                         //second node
 135                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 136                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 137 #endif
 138 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 139                         // third node
 140                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 141                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 142                         // four node
 143                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 144                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 145 #endif
 146
 147         };
 148
 149         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 150
 151         int needs_reset;
 152         unsigned bsp_apicid = 0;
 153 #if SET_FIDVID == 1
 154         struct cpuid_result cpuid1;
 155 #endif
 156
 157         if (!cpu_init_detectedx && boot_cpu()) {
 158                 /* Nothing special needs to be done to find bus 0 */
 159                 /* Allow the HT devices to be found */
 160
 161                 enumerate_ht_chain();
 162
 163                 /* Setup the rom access for 4M */
 164                 amd8111_enable_rom();
 165         }
 166
 167         if (bist == 0) {
 168                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 169         }
 170
 171 //      post_code(0x32);
 172
 173         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 174         uart_init();
 175         console_init();
 176
 177 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 178
 179         /* Halt if there was a built in self test failure */
 180         report_bist_failure(bist);
 181
 182         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 183
 184         setup_mb_resource_map();
 185 #if 0
 186         dump_pci_device(PCI_DEV(0, 0x18, 0));
 187         dump_pci_device(PCI_DEV(0, 0x19, 0));
 188 #endif
 189
 190         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 191
 192 #if CONFIG_MEM_TRAIN_SEQ == 1
 193         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 194 #endif
 195         setup_coherent_ht_domain(); // routing table and start other core0
 196
 197         wait_all_core0_started();
 198 #if CONFIG_LOGICAL_CPUS==1
 199         // It is said that we should start core1 after all core0 launched
 200         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 201          * So here need to make sure last core0 is started, esp for two way system,
 202          * (there may be apic id conflicts in that case)
 203          */
 204         start_other_cores();
 205         wait_all_other_cores_started(bsp_apicid);
 206 #endif
 207
 208         /* it will set up chains and store link pair for optimization later */
 209         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 210
 211 #if 0
 212         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 213         needs_reset = optimize_link_coherent_ht();
 214         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 215 #endif
 216
 217 #if SET_FIDVID == 1
 218         /* Check to see if processor is capable of changing FIDVID  */
 219         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 220         cpuid1 = cpuid(0x80000007);
 221         if( (cpuid1.edx & 0x6) == 0x6 ) {
 222
 223         {
 224                 /* Read FIDVID_STATUS */
 225                 msr_t msr;
 226                 msr=rdmsr(0xc0010042);
 227                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 228
 229         }
 230
 231         enable_fid_change();
 232
 233         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 234
 235         init_fidvid_bsp(bsp_apicid);
 236
 237         // show final fid and vid
 238         {
 239                 msr_t msr;
 240                 msr=rdmsr(0xc0010042);
 241                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 242
 243         }
 244
 245         } else {
 246                 print_debug("Changing FIDVID not supported\n");
 247         }
 248
 249 #endif
 250
 251 #if 1
 252         needs_reset = optimize_link_coherent_ht();
 253         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 254
 255         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 256         if (needs_reset) {
 257                 print_info("ht reset -\n");
 258                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 259         }
 260 #endif
 261         allow_all_aps_stop(bsp_apicid);
 262
 263         //It's the time to set ctrl in sysinfo now;
 264         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 265
 266         enable_smbus();
 267
 268 #if 0
 269         int i;
 270         for(i=0;i<4;i++) {
 271                 activate_spd_rom(&cpu[i]);
 272                 dump_smbus_registers();
 273         }
 274 #endif
 275
 276 #if 0
 277         for(i=1;i<256;i<<=1) {
 278                 change_i2c_mux(i);
 279                 dump_smbus_registers();
 280         }
 281 #endif
 282
 283         memreset_setup();
 284
 285         //do we need apci timer, tsc...., only debug need it for better output
 286         /* all ap stopped? */
 287 //        init_timer(); // Need to use TMICT to synconize FID/VID
 288
 289         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 290
 291 #if 0
 292         print_pci_devices();
 293 #endif
 294
 295 #if 0
 296 //        dump_pci_devices();
 297         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 298         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 299 #endif
 300
 301         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 302
 303 }
 304