src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #define RAMINIT_SYSINFO 1
   2 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   3
   4 #define SET_NB_CFG_54 1
   5
   6 //used by raminit
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 //used by incoherent_ht
  10 //#define K8_ALLOCATE_IO_RANGE 1
  11
  12 //used by init_cpus and fidvid
  13 #define K8_SET_FIDVID 0
  14 //if we want to wait for core1 done before DQS training, set it to 0
  15 #define K8_SET_FIDVID_CORE0_ONLY 1
  16
  17 #if CONFIG_K8_REV_F_SUPPORT == 1
  18 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  19 #endif
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <cpu/x86/lapic.h>
  29 #include "option_table.h"
  30 #include "pc80/mc146818rtc_early.c"
  31
  32 #if 0
  33 static void post_code(uint8_t value) {
  34 #if 1
  35         int i;
  36         for(i=0;i<0x80000;i++) {
  37                 outb(value, 0x80);
  38         }
  39 #endif
  40 }
  41 #endif
  42 #include "pc80/serial.c"
  43 #include "arch/i386/lib/console.c"
  44 #include <cpu/amd/model_fxx_rev.h>
  45 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  46 #include "northbridge/amd/amdk8/raminit.h"
  47 #include "cpu/amd/model_fxx/apic_timer.c"
  48
  49 #include "cpu/x86/lapic/boot_cpu.c"
  50 #include "northbridge/amd/amdk8/reset_test.c"
  51
  52 #include "cpu/x86/bist.h"
  53
  54 #include "lib/delay.c"
  55
  56 #include "northbridge/amd/amdk8/debug.c"
  57 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  58 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  59
  60 #include "northbridge/amd/amdk8/setup_resource_map.c"
  61
  62 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  63
  64 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  65
  66 static void memreset_setup(void)
  67 {
  68         //GPIO on amd8111 to enable MEMRST ????
  69         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  70         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  71 }
  72
  73 static void memreset(int controllers, const struct mem_controller *ctrl)
  74 {
  75 }
  76
  77 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  78 {
  79 #define SMBUS_HUB 0x18
  80         int ret,i;
  81         unsigned device=(ctrl->channel0[0])>>8;
  82         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  83         i=2;
  84         do {
  85                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  86         } while ((ret!=0) && (i-->0));
  87
  88         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  89 }
  90 #if 0
  91 static inline void change_i2c_mux(unsigned device)
  92 {
  93 #define SMBUS_HUB 0x18
  94         int ret, i;
  95         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
  96         i=2;
  97         do {
  98                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  99                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
 100         } while ((ret!=0) && (i-->0));
 101         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
 102         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
 103 }
 104 #endif
 105
 106 static inline int spd_read_byte(unsigned device, unsigned address)
 107 {
 108         return smbus_read_byte(device, address);
 109 }
 110
 111 #include "northbridge/amd/amdk8/amdk8.h"
 112 #include "northbridge/amd/amdk8/coherent_ht.c"
 113
 114 #include "northbridge/amd/amdk8/incoherent_ht.c"
 115
 116 #include "northbridge/amd/amdk8/raminit_f.c"
 117
 118 #include "lib/generic_sdram.c"
 119
 120  /* tyan does not want the default */
 121 #include "resourcemap.c"
 122
 123 #include "cpu/amd/dualcore/dualcore.c"
 124
 125 #define RC0 ((1<<0)<<8)
 126 #define RC1 ((1<<1)<<8)
 127 #define RC2 ((1<<2)<<8)
 128 #define RC3 ((1<<3)<<8)
 129
 130 #define DIMM0 0x50
 131 #define DIMM1 0x51
 132 #define DIMM2 0x52
 133 #define DIMM3 0x53
 134 #define DIMM4 0x54
 135 #define DIMM5 0x55
 136 #define DIMM6 0x56
 137 #define DIMM7 0x57
 138
 139 #include "cpu/amd/car/copy_and_run.c"
 140 #include "cpu/amd/car/post_cache_as_ram.c"
 141
 142 #include "cpu/amd/model_fxx/init_cpus.c"
 143
 144 #include "cpu/amd/model_fxx/fidvid.c"
 145
 146 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 147 #include "northbridge/amd/amdk8/early_ht.c"
 148
 149 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 150 {
 151         static const uint16_t spd_addr[] = {
 152                         //first node
 153                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 154                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 155 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 156                         //second node
 157                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 158                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 159 #endif
 160 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 161                         // third node
 162                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 163                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 164                         // four node
 165                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 166                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 167 #endif
 168
 169         };
 170
 171         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 172
 173         int needs_reset;
 174         unsigned bsp_apicid = 0;
 175 #if K8_SET_FIDVID == 1
 176         struct cpuid_result cpuid1;
 177 #endif
 178
 179         if (!cpu_init_detectedx && boot_cpu()) {
 180                 /* Nothing special needs to be done to find bus 0 */
 181                 /* Allow the HT devices to be found */
 182
 183                 enumerate_ht_chain();
 184
 185                 /* Setup the rom access for 4M */
 186                 amd8111_enable_rom();
 187         }
 188
 189         if (bist == 0) {
 190                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 191         }
 192
 193 //      post_code(0x32);
 194
 195         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 196         uart_init();
 197         console_init();
 198
 199 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 200
 201         /* Halt if there was a built in self test failure */
 202         report_bist_failure(bist);
 203
 204         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 205
 206         setup_mb_resource_map();
 207 #if 0
 208         dump_pci_device(PCI_DEV(0, 0x18, 0));
 209         dump_pci_device(PCI_DEV(0, 0x19, 0));
 210 #endif
 211
 212         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 213
 214 #if CONFIG_MEM_TRAIN_SEQ == 1
 215         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 216 #endif
 217         setup_coherent_ht_domain(); // routing table and start other core0
 218
 219         wait_all_core0_started();
 220 #if CONFIG_LOGICAL_CPUS==1
 221         // It is said that we should start core1 after all core0 launched
 222         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 223          * So here need to make sure last core0 is started, esp for two way system,
 224          * (there may be apic id conflicts in that case)
 225          */
 226         start_other_cores();
 227         wait_all_other_cores_started(bsp_apicid);
 228 #endif
 229
 230         /* it will set up chains and store link pair for optimization later */
 231         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 232
 233 #if 0
 234         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 235         needs_reset = optimize_link_coherent_ht();
 236         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 237 #endif
 238
 239 #if K8_SET_FIDVID == 1
 240         /* Check to see if processor is capable of changing FIDVID  */
 241         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 242         cpuid1 = cpuid(0x80000007);
 243         if( (cpuid1.edx & 0x6) == 0x6 ) {
 244
 245         {
 246                 /* Read FIDVID_STATUS */
 247                 msr_t msr;
 248                 msr=rdmsr(0xc0010042);
 249                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 250
 251         }
 252
 253         enable_fid_change();
 254
 255         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 256
 257         init_fidvid_bsp(bsp_apicid);
 258
 259         // show final fid and vid
 260         {
 261                 msr_t msr;
 262                 msr=rdmsr(0xc0010042);
 263                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 264
 265         }
 266
 267         } else {
 268                 print_debug("Changing FIDVID not supported\n");
 269         }
 270
 271 #endif
 272
 273 #if 1
 274         needs_reset = optimize_link_coherent_ht();
 275         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 276
 277         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 278         if (needs_reset) {
 279                 print_info("ht reset -\r\n");
 280                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 281         }
 282 #endif
 283         allow_all_aps_stop(bsp_apicid);
 284
 285         //It's the time to set ctrl in sysinfo now;
 286         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 287
 288         enable_smbus();
 289
 290 #if 0
 291         int i;
 292         for(i=0;i<4;i++) {
 293                 activate_spd_rom(&cpu[i]);
 294                 dump_smbus_registers();
 295         }
 296 #endif
 297
 298 #if 0
 299         for(i=1;i<256;i<<=1) {
 300                 change_i2c_mux(i);
 301                 dump_smbus_registers();
 302         }
 303 #endif
 304
 305         memreset_setup();
 306
 307         //do we need apci timer, tsc...., only debug need it for better output
 308         /* all ap stopped? */
 309 //        init_timer(); // Need to use TMICT to synconize FID/VID
 310
 311         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 312
 313 #if 0
 314         print_pci_devices();
 315 #endif
 316
 317 #if 0
 318 //        dump_pci_devices();
 319         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 320         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 321 #endif
 322
 323         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 324
 325 }
 326