src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_ALLOCATE_IO_RANGE 1
  14
  15 //used by init_cpus and fidvid
  16 #define K8_SET_FIDVID 0
  17 //if we want to wait for core1 done before DQS training, set it to 0
  18 #define K8_SET_FIDVID_CORE0_ONLY 1
  19
  20 #if CONFIG_K8_REV_F_SUPPORT == 1
  21 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  22 #endif
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <device/pci_def.h>
  27 #include <device/pci_ids.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include "option_table.h"
  33 #include "pc80/mc146818rtc_early.c"
  34
  35
  36 #if 0
  37 static void post_code(uint8_t value) {
  38 #if 1
  39         int i;
  40         for(i=0;i<0x80000;i++) {
  41                 outb(value, 0x80);
  42         }
  43 #endif
  44 }
  45 #endif
  46 #if CONFIG_USE_FAILOVER_IMAGE==0
  47 #include "pc80/serial.c"
  48 #include "arch/i386/lib/console.c"
  49 #include <cpu/amd/model_fxx_rev.h>
  50 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  51 #include "northbridge/amd/amdk8/raminit.h"
  52 #include "cpu/amd/model_fxx/apic_timer.c"
  53 #endif
  54
  55
  56
  57 #include "cpu/x86/lapic/boot_cpu.c"
  58 #include "northbridge/amd/amdk8/reset_test.c"
  59
  60 #if CONFIG_USE_FAILOVER_IMAGE==0
  61 #include "cpu/x86/bist.h"
  62
  63 #include "lib/delay.c"
  64
  65 #include "northbridge/amd/amdk8/debug.c"
  66 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  67 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  68
  69 #include "northbridge/amd/amdk8/setup_resource_map.c"
  70
  71 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  72
  73 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  74
  75 static void memreset_setup(void)
  76 {
  77         //GPIO on amd8111 to enable MEMRST ????
  78         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  79         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  80 }
  81
  82 static void memreset(int controllers, const struct mem_controller *ctrl)
  83 {
  84 }
  85
  86 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  87 {
  88 #define SMBUS_HUB 0x18
  89         int ret,i;
  90         unsigned device=(ctrl->channel0[0])>>8;
  91         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  92         i=2;
  93         do {
  94                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  95         } while ((ret!=0) && (i-->0));
  96
  97         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  98 }
  99 #if 0
 100 static inline void change_i2c_mux(unsigned device)
 101 {
 102 #define SMBUS_HUB 0x18
 103         int ret, i;
 104         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
 105         i=2;
 106         do {
 107                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 108                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
 109         } while ((ret!=0) && (i-->0));
 110         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
 111         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
 112 }
 113 #endif
 114
 115 static inline int spd_read_byte(unsigned device, unsigned address)
 116 {
 117         return smbus_read_byte(device, address);
 118 }
 119
 120 #include "northbridge/amd/amdk8/amdk8.h"
 121 #include "northbridge/amd/amdk8/coherent_ht.c"
 122
 123 #include "northbridge/amd/amdk8/incoherent_ht.c"
 124
 125 #include "northbridge/amd/amdk8/raminit_f.c"
 126
 127 #include "lib/generic_sdram.c"
 128
 129  /* tyan does not want the default */
 130 #include "resourcemap.c"
 131
 132 #include "cpu/amd/dualcore/dualcore.c"
 133
 134 #define RC0 ((1<<0)<<8)
 135 #define RC1 ((1<<1)<<8)
 136 #define RC2 ((1<<2)<<8)
 137 #define RC3 ((1<<3)<<8)
 138
 139 #define DIMM0 0x50
 140 #define DIMM1 0x51
 141 #define DIMM2 0x52
 142 #define DIMM3 0x53
 143 #define DIMM4 0x54
 144 #define DIMM5 0x55
 145 #define DIMM6 0x56
 146 #define DIMM7 0x57
 147
 148
 149 #include "cpu/amd/car/copy_and_run.c"
 150 #include "cpu/amd/car/post_cache_as_ram.c"
 151
 152 #include "cpu/amd/model_fxx/init_cpus.c"
 153
 154 #include "cpu/amd/model_fxx/fidvid.c"
 155 #endif
 156
 157 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 158
 159 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 160 #include "northbridge/amd/amdk8/early_ht.c"
 161
 162 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 163 {
 164
 165         unsigned last_boot_normal_x = last_boot_normal();
 166
 167         /* Is this a cpu only reset? or Is this a secondary cpu? */
 168         if ((cpu_init_detectedx) || (!boot_cpu())) {
 169                 if (last_boot_normal_x) {
 170                         goto normal_image;
 171                 } else {
 172                         goto fallback_image;
 173                 }
 174         }
 175
 176         /* Nothing special needs to be done to find bus 0 */
 177         /* Allow the HT devices to be found */
 178
 179         enumerate_ht_chain();
 180
 181         /* Setup the rom access for 4M */
 182         amd8111_enable_rom();
 183
 184         /* Is this a deliberate reset by the bios */
 185         if (bios_reset_detected() && last_boot_normal_x) {
 186                 goto normal_image;
 187         }
 188         /* This is the primary cpu how should I boot? */
 189         else if (do_normal_boot()) {
 190                 goto normal_image;
 191         }
 192         else {
 193                 goto fallback_image;
 194         }
 195  normal_image:
 196         __asm__ volatile ("jmp __normal_image"
 197                 : /* outputs */
 198                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 199                 );
 200
 201  fallback_image:
 202 #if CONFIG_HAVE_FAILOVER_BOOT==1
 203         __asm__ volatile ("jmp __fallback_image"
 204                 : /* outputs */
 205                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 206                 )
 207 #endif
 208         ;
 209 }
 210 #endif
 211
 212 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 213
 214 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 215 {
 216 #if CONFIG_HAVE_FAILOVER_BOOT==1
 217     #if CONFIG_USE_FAILOVER_IMAGE==1
 218         failover_process(bist, cpu_init_detectedx);
 219     #else
 220         real_main(bist, cpu_init_detectedx);
 221     #endif
 222 #else
 223     #if CONFIG_USE_FALLBACK_IMAGE == 1
 224         failover_process(bist, cpu_init_detectedx);
 225     #endif
 226         real_main(bist, cpu_init_detectedx);
 227 #endif
 228 }
 229
 230 #if CONFIG_USE_FAILOVER_IMAGE==0
 231
 232 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 233 {
 234         static const uint16_t spd_addr[] = {
 235                         //first node
 236                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 237                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 238 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 239                         //second node
 240                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 241                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 242 #endif
 243 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 244                         // third node
 245                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 246                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 247                         // four node
 248                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 249                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 250 #endif
 251
 252         };
 253
 254         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 255
 256         int needs_reset;
 257         unsigned bsp_apicid = 0;
 258 #if K8_SET_FIDVID == 1
 259         struct cpuid_result cpuid1;
 260 #endif
 261
 262         if (bist == 0) {
 263                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 264         }
 265
 266 //      post_code(0x32);
 267
 268         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 269         uart_init();
 270         console_init();
 271
 272 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 273
 274         /* Halt if there was a built in self test failure */
 275         report_bist_failure(bist);
 276
 277         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 278
 279         setup_mb_resource_map();
 280 #if 0
 281         dump_pci_device(PCI_DEV(0, 0x18, 0));
 282         dump_pci_device(PCI_DEV(0, 0x19, 0));
 283 #endif
 284
 285         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 286
 287 #if CONFIG_MEM_TRAIN_SEQ == 1
 288         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 289 #endif
 290         setup_coherent_ht_domain(); // routing table and start other core0
 291
 292         wait_all_core0_started();
 293 #if CONFIG_LOGICAL_CPUS==1
 294         // It is said that we should start core1 after all core0 launched
 295         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 296          * So here need to make sure last core0 is started, esp for two way system,
 297          * (there may be apic id conflicts in that case)
 298          */
 299         start_other_cores();
 300         wait_all_other_cores_started(bsp_apicid);
 301 #endif
 302
 303         /* it will set up chains and store link pair for optimization later */
 304         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 305
 306 #if 0
 307         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 308         needs_reset = optimize_link_coherent_ht();
 309         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 310 #endif
 311
 312 #if K8_SET_FIDVID == 1
 313         /* Check to see if processor is capable of changing FIDVID  */
 314         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 315         cpuid1 = cpuid(0x80000007);
 316         if( (cpuid1.edx & 0x6) == 0x6 ) {
 317
 318         {
 319                 /* Read FIDVID_STATUS */
 320                 msr_t msr;
 321                 msr=rdmsr(0xc0010042);
 322                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 323
 324         }
 325
 326         enable_fid_change();
 327
 328         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 329
 330         init_fidvid_bsp(bsp_apicid);
 331
 332         // show final fid and vid
 333         {
 334                 msr_t msr;
 335                 msr=rdmsr(0xc0010042);
 336                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 337
 338         }
 339
 340         } else {
 341                 print_debug("Changing FIDVID not supported\n");
 342         }
 343
 344 #endif
 345
 346 #if 1
 347         needs_reset = optimize_link_coherent_ht();
 348         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 349
 350         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 351         if (needs_reset) {
 352                 print_info("ht reset -\r\n");
 353                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 354         }
 355 #endif
 356         allow_all_aps_stop(bsp_apicid);
 357
 358         //It's the time to set ctrl in sysinfo now;
 359         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 360
 361         enable_smbus();
 362
 363 #if 0
 364         int i;
 365         for(i=0;i<4;i++) {
 366                 activate_spd_rom(&cpu[i]);
 367                 dump_smbus_registers();
 368         }
 369 #endif
 370
 371 #if 0
 372         for(i=1;i<256;i<<=1) {
 373                 change_i2c_mux(i);
 374                 dump_smbus_registers();
 375         }
 376 #endif
 377
 378         memreset_setup();
 379
 380         //do we need apci timer, tsc...., only debug need it for better output
 381         /* all ap stopped? */
 382 //        init_timer(); // Need to use TMICT to synconize FID/VID
 383
 384         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 385
 386 #if 0
 387         print_pci_devices();
 388 #endif
 389
 390 #if 0
 391 //        dump_pci_devices();
 392         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 393         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 394 #endif
 395
 396         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 397
 398 }
 399 #endif