4 #define RAMINIT_SYSINFO 1
5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
7 #define SET_NB_CFG_54 1
10 #define QRANK_DIMM_SUPPORT 1
12 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
15 #include <device/pci_def.h>
16 #include <device/pci_ids.h>
18 #include <device/pnp_def.h>
19 #include <arch/romcc_io.h>
20 #include <cpu/x86/lapic.h>
21 #include "option_table.h"
22 #include "pc80/mc146818rtc_early.c"
23 #include "pc80/serial.c"
25 #if CONFIG_USE_INIT == 0
26 #include "lib/memcpy.c"
29 #include "arch/i386/lib/console.c"
32 static void post_code(uint8_t value) {
35 for(i=0;i<0x80000;i++) {
42 #include <cpu/amd/model_fxx_rev.h>
43 #include "northbridge/amd/amdk8/raminit.h"
44 #include "cpu/amd/model_fxx/apic_timer.c"
46 #include "lib/delay.c"
49 //#include "cpu/x86/lapic/boot_cpu.c"
50 #include "northbridge/amd/amdk8/reset_test.c"
52 #include "northbridge/amd/amdk8/debug.c"
54 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
56 #include "northbridge/amd/amdk8/amdk8_f.h"
58 #include "cpu/x86/mtrr.h"
59 #include "cpu/amd/mtrr.h"
60 #include "cpu/x86/tsc.h"
62 #include "northbridge/amd/amdk8/amdk8_f_pci.c"
63 #include "northbridge/amd/amdk8/raminit_f_dqs.c"
65 static inline unsigned get_nodes(void)
67 return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
70 #include "cpu/amd/dualcore/dualcore.c"
72 void hardwaremain(int ret_addr)
74 struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
75 struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
77 struct node_core_id id;
79 id = get_node_core_id_x();
81 #if CONFIG_USE_PRINTK_IN_CAR
82 printk_debug("CODE IN CACHE ON NODE: %02x\n");
84 print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
87 train_ram(id.nodeid, sysinfo, sysinfox);
90 go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
103 uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
111 void x86_exception(struct eregs *info)