1 include /config/failovercalculation.lb
6 ## Build the objects we have code for in this directory.
13 #needed by irq_tables and mptable and acpi_tables
25 # object acpi_tables.o
27 # if SB_HT_CHAIN_ON_BUS0
34 # if SB_HT_CHAIN_ON_BUS0
46 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
47 action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
48 action "mv dsdt_lb.hex dsdt.c"
52 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
56 depends "$(MAINBOARD)/dx/pci2.asl"
57 action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
58 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
59 action "mv pci2.hex ssdt2.c"
63 depends "$(MAINBOARD)/dx/pci3.asl"
64 action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
65 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
66 action "mv pci3.hex ssdt3.c"
70 depends "$(MAINBOARD)/dx/pci4.asl"
71 action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
72 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
73 action "mv pci4.hex ssdt4.c"
80 # compile cache_as_ram.c to auto.o
81 makerule ./cache_as_ram_auto.o
82 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
83 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
87 #compile cache_as_ram.c to auto.inc
88 makerule ./cache_as_ram_auto.inc
89 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
90 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
91 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
92 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
98 if CONFIG_AP_CODE_IN_CAR
100 depends "$(MAINBOARD)/apc_auto.c option_table.h"
101 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
103 ldscript /arch/i386/init/ldscript_apc.lb
108 ## Build our 16 bit and 32 bit coreboot entry code
111 if HAVE_FAILOVER_BOOT
112 if USE_FAILOVER_IMAGE
113 mainboardinit cpu/x86/16bit/entry16.inc
114 ldscript /cpu/x86/16bit/entry16.lds
117 if USE_FALLBACK_IMAGE
118 mainboardinit cpu/x86/16bit/entry16.inc
119 ldscript /cpu/x86/16bit/entry16.lds
123 mainboardinit cpu/x86/32bit/entry32.inc
125 ldscript /cpu/x86/32bit/entry32.lds
129 ldscript /cpu/amd/car/cache_as_ram.lds
133 ## Build our reset vector (This is where coreboot is entered)
135 if HAVE_FAILOVER_BOOT
136 if USE_FAILOVER_IMAGE
137 mainboardinit cpu/x86/16bit/reset16.inc
138 ldscript /cpu/x86/16bit/reset16.lds
140 mainboardinit cpu/x86/32bit/reset32.inc
141 ldscript /cpu/x86/32bit/reset32.lds
144 if USE_FALLBACK_IMAGE
145 mainboardinit cpu/x86/16bit/reset16.inc
146 ldscript /cpu/x86/16bit/reset16.lds
148 mainboardinit cpu/x86/32bit/reset32.inc
149 ldscript /cpu/x86/32bit/reset32.lds
154 ## Include an id string (For safe flashing)
156 mainboardinit arch/i386/lib/id.inc
157 ldscript /arch/i386/lib/id.lds
160 ## Setup Cache-As-Ram
162 mainboardinit cpu/amd/car/cache_as_ram.inc
165 ### This is the early phase of coreboot startup
166 ### Things are delicate and we test to see if we should
167 ### failover to another image.
169 if HAVE_FAILOVER_BOOT
170 if USE_FAILOVER_IMAGE
171 ldscript /arch/i386/lib/failover_failover.lds
174 if USE_FALLBACK_IMAGE
175 ldscript /arch/i386/lib/failover.lds
180 ### O.k. We aren't just an intermediary anymore!
187 initobject cache_as_ram_auto.o
189 mainboardinit ./cache_as_ram_auto.inc
193 ## Include the secondary Configuration files
197 # sample config for amd/serengeti_cheetah
198 chip northbridge/amd/amdk8/root_complex
199 device apic_cluster 0 on
200 chip cpu/amd/socket_F
204 device pci_domain 0 on
205 chip northbridge/amd/amdk8
206 device pci 18.0 on # northbridge
207 # devices on link 0, link 0 == LDT 0
208 chip southbridge/amd/amd8132
209 # the on/off keyword is mandatory
210 device pci 0.0 on end
211 device pci 0.1 on end
212 device pci 1.0 on end
213 device pci 1.1 on end
215 chip southbridge/amd/amd8111
216 # this "device pci 0.0" is the parent the next one
219 device pci 0.0 on end
220 device pci 0.1 on end
221 device pci 0.2 off end
222 device pci 1.0 off end
225 chip superio/winbond/w83627hf
226 device pnp 2e.0 off # Floppy
231 device pnp 2e.1 off # Parallel Port
235 device pnp 2e.2 on # Com1
239 device pnp 2e.3 off # Com2
243 device pnp 2e.5 on # Keyboard
249 device pnp 2e.6 off # CIR
252 device pnp 2e.7 off # GAME_MIDI_GIPO1
257 device pnp 2e.8 off end # GPIO2
258 device pnp 2e.9 off end # GPIO3
259 device pnp 2e.a off end # ACPI
260 device pnp 2e.b on # HW Monitor
266 device pci 1.1 on end
267 device pci 1.2 on end
269 chip drivers/i2c/i2cmux # pca9556 smbus mux
270 device i2c 18 on #0 pca9516 1
271 chip drivers/generic/generic #dimm 0-0-0
274 chip drivers/generic/generic #dimm 0-0-1
277 chip drivers/generic/generic #dimm 0-1-0
280 chip drivers/generic/generic #dimm 0-1-1
284 device i2c 18 on #1 pca9516 2
285 chip drivers/generic/generic #dimm 1-0-0
288 chip drivers/generic/generic #dimm 1-0-1
291 chip drivers/generic/generic #dimm 1-1-0
294 chip drivers/generic/generic #dimm 1-1-1
297 chip drivers/generic/generic #dimm 1-2-0
300 chip drivers/generic/generic #dimm 1-2-1
303 chip drivers/generic/generic #dimm 1-3-0
306 chip drivers/generic/generic #dimm 1-3-1
312 device pci 1.5 off end
313 device pci 1.6 off end
314 register "ide0_enable" = "1"
315 register "ide1_enable" = "1"
317 end # device pci 18.0
319 device pci 18.0 on end
320 device pci 18.0 on end
321 device pci 18.1 on end
322 device pci 18.2 on end
323 device pci 18.3 on end
325 chip northbridge/amd/amdk8
326 device pci 19.0 on # northbridge
327 chip southbridge/amd/amd8151
328 # the on/off keyword is mandatory
329 device pci 0.0 on end
330 device pci 1.0 on end
332 end # device pci 19.0
334 device pci 19.0 on end
335 device pci 19.0 on end
336 device pci 19.1 on end
337 device pci 19.2 on end
338 device pci 19.3 on end
343 # chip drivers/generic/debug
344 # device pnp 0.0 off end # chip name
345 # device pnp 0.1 on end # pci_regs_all
346 # device pnp 0.2 off end # mem
347 # device pnp 0.3 off end # cpuid
348 # device pnp 0.4 off end # smbus_regs_all
349 # device pnp 0.5 off end # dual core msr
350 # device pnp 0.6 off end # cache size
351 # device pnp 0.7 off end # tsc