2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FAILOVER_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
10 default ROM_SECTION_SIZE = FALLBACK_SIZE
11 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
13 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
14 default ROM_SECTION_OFFSET = 0
19 ## Compute the start location and size size of
20 ## The linuxBIOS bootloader.
22 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
26 ## Compute where this copy of linuxBIOS will start in the boot rom
28 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
31 ## Compute a range of ROM that can cached to speed up linuxBIOS,
34 ## XIP_ROM_SIZE must be a power of 2.
35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
37 default XIP_ROM_SIZE=65536
40 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 ## Build the objects we have code for in this directory.
59 #needed by irq_tables and mptable and acpi_tables
71 # object acpi_tables.o
73 # if SB_HT_CHAIN_ON_BUS0
80 # if SB_HT_CHAIN_ON_BUS0
92 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
93 action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
94 action "mv dsdt_lb.hex dsdt.c"
98 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
102 depends "$(MAINBOARD)/dx/pci2.asl"
103 action "iasl -tc $(MAINBOARD)/dx/pci2.asl"
104 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
105 action "mv pci2.hex ssdt2.c"
109 depends "$(MAINBOARD)/dx/pci3.asl"
110 action "iasl -tc $(MAINBOARD)/dx/pci3.asl"
111 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
112 action "mv pci3.hex ssdt3.c"
116 depends "$(MAINBOARD)/dx/pci4.asl"
117 action "iasl -tc $(MAINBOARD)/dx/pci4.asl"
118 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
119 action "mv pci4.hex ssdt4.c"
128 # compile cache_as_ram.c to auto.o
129 makerule ./cache_as_ram_auto.o
130 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
131 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
135 #compile cache_as_ram.c to auto.inc
136 makerule ./cache_as_ram_auto.inc
137 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
138 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
139 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
140 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
146 if USE_FAILOVER_IMAGE
148 if CONFIG_AP_CODE_IN_CAR
149 makerule ./apc_auto.o
150 depends "$(MAINBOARD)/apc_auto.c option_table.h"
151 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
153 ldscript /arch/i386/init/ldscript_apc.lb
158 ## Build our 16 bit and 32 bit linuxBIOS entry code
161 if HAVE_FAILOVER_BOOT
162 if USE_FAILOVER_IMAGE
163 mainboardinit cpu/x86/16bit/entry16.inc
164 ldscript /cpu/x86/16bit/entry16.lds
167 if USE_FALLBACK_IMAGE
168 mainboardinit cpu/x86/16bit/entry16.inc
169 ldscript /cpu/x86/16bit/entry16.lds
173 mainboardinit cpu/x86/32bit/entry32.inc
176 ldscript /cpu/x86/32bit/entry32.lds
180 ldscript /cpu/amd/car/cache_as_ram.lds
185 ## Build our reset vector (This is where linuxBIOS is entered)
187 if HAVE_FAILOVER_BOOT
188 if USE_FAILOVER_IMAGE
189 mainboardinit cpu/x86/16bit/reset16.inc
190 ldscript /cpu/x86/16bit/reset16.lds
192 mainboardinit cpu/x86/32bit/reset32.inc
193 ldscript /cpu/x86/32bit/reset32.lds
196 if USE_FALLBACK_IMAGE
197 mainboardinit cpu/x86/16bit/reset16.inc
198 ldscript /cpu/x86/16bit/reset16.lds
200 mainboardinit cpu/x86/32bit/reset32.inc
201 ldscript /cpu/x86/32bit/reset32.lds
206 ## Include an id string (For safe flashing)
208 mainboardinit arch/i386/lib/id.inc
209 ldscript /arch/i386/lib/id.lds
213 ## Setup Cache-As-Ram
215 mainboardinit cpu/amd/car/cache_as_ram.inc
219 ### This is the early phase of linuxBIOS startup
220 ### Things are delicate and we test to see if we should
221 ### failover to another image.
223 if HAVE_FAILOVER_BOOT
224 if USE_FAILOVER_IMAGE
226 ldscript /arch/i386/lib/failover_failover.lds
230 if USE_FALLBACK_IMAGE
232 ldscript /arch/i386/lib/failover.lds
238 ### O.k. We aren't just an intermediary anymore!
247 initobject cache_as_ram_auto.o
249 mainboardinit ./cache_as_ram_auto.inc
255 ## Include the secondary Configuration files
261 # sample config for amd/serengeti_cheetah
262 chip northbridge/amd/amdk8/root_complex
263 device apic_cluster 0 on
264 chip cpu/amd/socket_F
268 device pci_domain 0 on
269 chip northbridge/amd/amdk8
270 device pci 18.0 on # northbridge
271 # devices on link 0, link 0 == LDT 0
272 chip southbridge/amd/amd8132
273 # the on/off keyword is mandatory
274 device pci 0.0 on end
275 device pci 0.1 on end
276 device pci 1.0 on end
277 device pci 1.1 on end
279 chip southbridge/amd/amd8111
280 # this "device pci 0.0" is the parent the next one
283 device pci 0.0 on end
284 device pci 0.1 on end
285 device pci 0.2 off end
286 device pci 1.0 off end
289 chip superio/winbond/w83627hf
290 device pnp 2e.0 off # Floppy
295 device pnp 2e.1 off # Parallel Port
299 device pnp 2e.2 on # Com1
303 device pnp 2e.3 off # Com2
307 device pnp 2e.5 on # Keyboard
313 device pnp 2e.6 off # CIR
316 device pnp 2e.7 off # GAME_MIDI_GIPO1
321 device pnp 2e.8 off end # GPIO2
322 device pnp 2e.9 off end # GPIO3
323 device pnp 2e.a off end # ACPI
324 device pnp 2e.b on # HW Monitor
330 device pci 1.1 on end
331 device pci 1.2 on end
333 chip drivers/i2c/i2cmux # pca9556 smbus mux
334 device i2c 18 on #0 pca9516 1
335 chip drivers/generic/generic #dimm 0-0-0
338 chip drivers/generic/generic #dimm 0-0-1
341 chip drivers/generic/generic #dimm 0-1-0
344 chip drivers/generic/generic #dimm 0-1-1
348 device i2c 18 on #1 pca9516 2
349 chip drivers/generic/generic #dimm 1-0-0
352 chip drivers/generic/generic #dimm 1-0-1
355 chip drivers/generic/generic #dimm 1-1-0
358 chip drivers/generic/generic #dimm 1-1-1
361 chip drivers/generic/generic #dimm 1-2-0
364 chip drivers/generic/generic #dimm 1-2-1
367 chip drivers/generic/generic #dimm 1-3-0
370 chip drivers/generic/generic #dimm 1-3-1
376 device pci 1.5 off end
377 device pci 1.6 off end
378 register "ide0_enable" = "1"
379 register "ide1_enable" = "1"
381 end # device pci 18.0
383 device pci 18.0 on end
384 device pci 18.0 on end
385 device pci 18.1 on end
386 device pci 18.2 on end
387 device pci 18.3 on end
389 chip northbridge/amd/amdk8
390 device pci 19.0 on # northbridge
391 chip southbridge/amd/amd8151
392 # the on/off keyword is mandatory
393 device pci 0.0 on end
394 device pci 1.0 on end
396 end # device pci 19.0
398 device pci 19.0 on end
399 device pci 19.0 on end
400 device pci 19.1 on end
401 device pci 19.2 on end
402 device pci 19.3 on end
407 # chip drivers/generic/debug
408 # device pnp 0.0 off end # chip name
409 # device pnp 0.1 on end # pci_regs_all
410 # device pnp 0.2 off end # mem
411 # device pnp 0.3 off end # cpuid
412 # device pnp 0.4 off end # smbus_regs_all
413 # device pnp 0.5 off end # dual core msr
414 # device pnp 0.6 off end # cache size
415 # device pnp 0.7 off end # tsc