2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FAILOVER_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
10 default ROM_SECTION_SIZE = FALLBACK_SIZE
11 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
13 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
14 default ROM_SECTION_OFFSET = 0
19 ## Compute the start location and size size of
20 ## The coreboot bootloader.
22 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
26 ## Compute where this copy of coreboot will start in the boot rom
28 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
31 ## Compute a range of ROM that can cached to speed up coreboot,
34 ## XIP_ROM_SIZE must be a power of 2.
35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
37 default XIP_ROM_SIZE=65536
40 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 ## Build the objects we have code for in this directory.
59 #needed by irq_tables and mptable and acpi_tables
71 # object acpi_tables.o
73 # if SB_HT_CHAIN_ON_BUS0
80 # if SB_HT_CHAIN_ON_BUS0
92 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
93 action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
94 action "mv dsdt_lb.hex dsdt.c"
98 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
102 depends "$(MAINBOARD)/dx/pci2.asl"
103 action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
104 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
105 action "mv pci2.hex ssdt2.c"
109 depends "$(MAINBOARD)/dx/pci3.asl"
110 action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
111 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
112 action "mv pci3.hex ssdt3.c"
116 depends "$(MAINBOARD)/dx/pci4.asl"
117 action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
118 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
119 action "mv pci4.hex ssdt4.c"
126 # compile cache_as_ram.c to auto.o
127 makerule ./cache_as_ram_auto.o
128 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
129 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
133 #compile cache_as_ram.c to auto.inc
134 makerule ./cache_as_ram_auto.inc
135 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
136 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
137 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
138 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
142 if USE_FAILOVER_IMAGE
144 if CONFIG_AP_CODE_IN_CAR
145 makerule ./apc_auto.o
146 depends "$(MAINBOARD)/apc_auto.c option_table.h"
147 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
149 ldscript /arch/i386/init/ldscript_apc.lb
154 ## Build our 16 bit and 32 bit coreboot entry code
157 if HAVE_FAILOVER_BOOT
158 if USE_FAILOVER_IMAGE
159 mainboardinit cpu/x86/16bit/entry16.inc
160 ldscript /cpu/x86/16bit/entry16.lds
163 if USE_FALLBACK_IMAGE
164 mainboardinit cpu/x86/16bit/entry16.inc
165 ldscript /cpu/x86/16bit/entry16.lds
169 mainboardinit cpu/x86/32bit/entry32.inc
171 ldscript /cpu/x86/32bit/entry32.lds
175 ldscript /cpu/amd/car/cache_as_ram.lds
179 ## Build our reset vector (This is where coreboot is entered)
181 if HAVE_FAILOVER_BOOT
182 if USE_FAILOVER_IMAGE
183 mainboardinit cpu/x86/16bit/reset16.inc
184 ldscript /cpu/x86/16bit/reset16.lds
186 mainboardinit cpu/x86/32bit/reset32.inc
187 ldscript /cpu/x86/32bit/reset32.lds
190 if USE_FALLBACK_IMAGE
191 mainboardinit cpu/x86/16bit/reset16.inc
192 ldscript /cpu/x86/16bit/reset16.lds
194 mainboardinit cpu/x86/32bit/reset32.inc
195 ldscript /cpu/x86/32bit/reset32.lds
200 ## Include an id string (For safe flashing)
202 mainboardinit arch/i386/lib/id.inc
203 ldscript /arch/i386/lib/id.lds
206 ## Setup Cache-As-Ram
208 mainboardinit cpu/amd/car/cache_as_ram.inc
211 ### This is the early phase of coreboot startup
212 ### Things are delicate and we test to see if we should
213 ### failover to another image.
215 if HAVE_FAILOVER_BOOT
216 if USE_FAILOVER_IMAGE
217 ldscript /arch/i386/lib/failover_failover.lds
220 if USE_FALLBACK_IMAGE
221 ldscript /arch/i386/lib/failover.lds
226 ### O.k. We aren't just an intermediary anymore!
233 initobject cache_as_ram_auto.o
235 mainboardinit ./cache_as_ram_auto.inc
239 ## Include the secondary Configuration files
243 # sample config for amd/serengeti_cheetah
244 chip northbridge/amd/amdk8/root_complex
245 device apic_cluster 0 on
246 chip cpu/amd/socket_F
250 device pci_domain 0 on
251 chip northbridge/amd/amdk8
252 device pci 18.0 on # northbridge
253 # devices on link 0, link 0 == LDT 0
254 chip southbridge/amd/amd8132
255 # the on/off keyword is mandatory
256 device pci 0.0 on end
257 device pci 0.1 on end
258 device pci 1.0 on end
259 device pci 1.1 on end
261 chip southbridge/amd/amd8111
262 # this "device pci 0.0" is the parent the next one
265 device pci 0.0 on end
266 device pci 0.1 on end
267 device pci 0.2 off end
268 device pci 1.0 off end
271 chip superio/winbond/w83627hf
272 device pnp 2e.0 off # Floppy
277 device pnp 2e.1 off # Parallel Port
281 device pnp 2e.2 on # Com1
285 device pnp 2e.3 off # Com2
289 device pnp 2e.5 on # Keyboard
295 device pnp 2e.6 off # CIR
298 device pnp 2e.7 off # GAME_MIDI_GIPO1
303 device pnp 2e.8 off end # GPIO2
304 device pnp 2e.9 off end # GPIO3
305 device pnp 2e.a off end # ACPI
306 device pnp 2e.b on # HW Monitor
312 device pci 1.1 on end
313 device pci 1.2 on end
315 chip drivers/i2c/i2cmux # pca9556 smbus mux
316 device i2c 18 on #0 pca9516 1
317 chip drivers/generic/generic #dimm 0-0-0
320 chip drivers/generic/generic #dimm 0-0-1
323 chip drivers/generic/generic #dimm 0-1-0
326 chip drivers/generic/generic #dimm 0-1-1
330 device i2c 18 on #1 pca9516 2
331 chip drivers/generic/generic #dimm 1-0-0
334 chip drivers/generic/generic #dimm 1-0-1
337 chip drivers/generic/generic #dimm 1-1-0
340 chip drivers/generic/generic #dimm 1-1-1
343 chip drivers/generic/generic #dimm 1-2-0
346 chip drivers/generic/generic #dimm 1-2-1
349 chip drivers/generic/generic #dimm 1-3-0
352 chip drivers/generic/generic #dimm 1-3-1
358 device pci 1.5 off end
359 device pci 1.6 off end
360 register "ide0_enable" = "1"
361 register "ide1_enable" = "1"
363 end # device pci 18.0
365 device pci 18.0 on end
366 device pci 18.0 on end
367 device pci 18.1 on end
368 device pci 18.2 on end
369 device pci 18.3 on end
371 chip northbridge/amd/amdk8
372 device pci 19.0 on # northbridge
373 chip southbridge/amd/amd8151
374 # the on/off keyword is mandatory
375 device pci 0.0 on end
376 device pci 1.0 on end
378 end # device pci 19.0
380 device pci 19.0 on end
381 device pci 19.0 on end
382 device pci 19.1 on end
383 device pci 19.2 on end
384 device pci 19.3 on end
389 # chip drivers/generic/debug
390 # device pnp 0.0 off end # chip name
391 # device pnp 0.1 on end # pci_regs_all
392 # device pnp 0.2 off end # mem
393 # device pnp 0.3 off end # cpuid
394 # device pnp 0.4 off end # smbus_regs_all
395 # device pnp 0.5 off end # dual core msr
396 # device pnp 0.6 off end # cache size
397 # device pnp 0.7 off end # tsc