src/mainboard/amd/serenade/auto.c

   1 #define ASSEMBLY 1
   2 #define DEFAULT_CONSOLE_LOGLEVEL 8
   3 #define MAXIMUM_CONSOLE_LOGLEVEL 8
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <arch/cpu.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "northbridge/amd/amdk8/cpu_rev.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 static void hard_reset(void)
  32 {
  33         set_bios_reset();
  34
  35         /* enable cf9 */
  36         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  37         /* reset */
  38         outb(0x0e, 0x0cf9);
  39 }
  40
  41 static void soft_reset(void)
  42 {
  43         set_bios_reset();
  44         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  45 }
  46
  47 /*
  48  * GPIO16 of 8111 will control H0_MEMRESET_L
  49  * GPIO17 of 8111 will control H1_MEMRESET_L
  50  */
  51 static void memreset_setup(void)
  52 {
  53         if (is_cpu_pre_c0()) {
  54                 /* Set the memreset low */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  56                 /* Ensure the BIOS has control of the memory lines */
  57                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  58         } else {
  59                 /* Ensure the CPU has controll of the memory lines */
  60                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  61         }
  62 }
  63
  64 static void memreset(int controllers, const struct mem_controller *ctrl)
  65 {
  66         if (is_cpu_pre_c0()) {
  67                 udelay(800);
  68                 /* Set memreset_high */
  69                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  70                 udelay(90);
  71         }
  72 }
  73
  74 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  75 {
  76         /* Routing Table Node i
  77          *
  78          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  79          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  80          *
  81          * [ 0: 3] Request Route
  82          *     [0] Route to this node
  83          *     [1] Route to Link 0
  84          *     [2] Route to Link 1
  85          *     [3] Route to Link 2
  86          * [11: 8] Response Route
  87          *     [0] Route to this node
  88          *     [1] Route to Link 0
  89          *     [2] Route to Link 1
  90          *     [3] Route to Link 2
  91          * [19:16] Broadcast route
  92          *     [0] Route to this node
  93          *     [1] Route to Link 0
  94          *     [2] Route to Link 1
  95          *     [3] Route to Link 2
  96          */
  97
  98         uint32_t ret = 0x00010101; /* default row entry */
  99
 100         /* CPU0 LDT0 <-> LDT0 CPU1 */
 101         static const unsigned int rows_2p[2][2] = {
 102                 { 0x00030101, 0x00010202 },
 103                 { 0x00010202, 0x00030101 }
 104         };
 105
 106         if (maxnodes > 2) {
 107                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 108                 maxnodes = 2;
 109         }
 110
 111         if (!(node >= maxnodes || row >= maxnodes)) {
 112                 ret = rows_2p[node][row];
 113         }
 114
 115         return ret;
 116 }
 117
 118 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 119 {
 120         /* nothing to do */
 121 }
 122
 123 static inline int spd_read_byte(unsigned device, unsigned address)
 124 {
 125         return smbus_read_byte(device, address);
 126 }
 127
 128 #include "northbridge/amd/amdk8/raminit.c"
 129 #include "northbridge/amd/amdk8/coherent_ht.c"
 130 #include "sdram/generic_sdram.c"
 131 #include "resourcemap.c"
 132
 133 #define FIRST_CPU  1
 134 #define SECOND_CPU 1
 135 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 136 static void main(unsigned long bist)
 137 {
 138         static const struct mem_controller cpu[] = {
 139 #if FIRST_CPU
 140                 {
 141                         .node_id = 0,
 142                         .f0 = PCI_DEV(0, 0x18, 0),
 143                         .f1 = PCI_DEV(0, 0x18, 1),
 144                         .f2 = PCI_DEV(0, 0x18, 2),
 145                         .f3 = PCI_DEV(0, 0x18, 3),
 146                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 147                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 148                 },
 149 #endif
 150 #if SECOND_CPU
 151                 {
 152                         .node_id = 1,
 153                         .f0 = PCI_DEV(0, 0x19, 0),
 154                         .f1 = PCI_DEV(0, 0x19, 1),
 155                         .f2 = PCI_DEV(0, 0x19, 2),
 156                         .f3 = PCI_DEV(0, 0x19, 3),
 157                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 158                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 159                 },
 160 #endif
 161         };
 162
 163         int needs_reset;
 164         if (bist == 0) {
 165                 /* Skip this if there was a built in self test failure */
 166                 amd_early_mtrr_init();
 167                 enable_lapic();
 168                 init_timer();
 169                 /* Has this cpu already booted? */
 170                 if (cpu_init_detected()) {
 171                         asm volatile ("jmp __cpu_reset");
 172                 }
 173
 174                 distinguish_cpu_resets();
 175                 if (!boot_cpu()) {
 176                         stop_this_cpu();
 177                 }
 178         }
 179         /* Setup the console */
 180         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 181         uart_init();
 182         console_init();
 183
 184         /* Halt if there was a built in self test failure */
 185         report_bist_failure(bist);
 186
 187 #if 0
 188         print_pci_devices();
 189 #endif
 190
 191         setup_amd_serenade_resource_map();
 192         needs_reset = setup_coherent_ht_domain();
 193         /* non-coherent HT is on LDT2 */
 194         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xC0);
 195         if (needs_reset) {
 196                 print_info("ht reset -\r\n");
 197                 soft_reset();
 198         }
 199
 200 #if 1
 201         print_pci_devices();
 202 #endif
 203
 204         enable_smbus();
 205
 206 #if 0
 207         dump_spd_registers(&cpu[0]);
 208 #endif
 209
 210         memreset_setup();
 211         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 212
 213 #if 0
 214         dump_pci_devices();
 215 #endif
 216
 217         print_pci_devices();
 218
 219 #if 0
 220         dump_pci_device(PCI_DEV(0, 0x18, 2));
 221 #endif
 222
 223 #if 0
 224         /* Check the first 1M */
 225         ram_check(0x00000000, 0x001000000);
 226 #endif
 227
 228 }