2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
6 #include <console/console.h>
7 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
8 #include "cpu/x86/bist.h"
9 #include "cpu/x86/msr.h"
10 #include <cpu/amd/gx2def.h>
11 #include <cpu/amd/geode_post_code.h>
13 #include "southbridge/amd/cs5536/early_smbus.c"
14 #include "southbridge/amd/cs5536/early_setup.c"
16 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
18 static inline int spd_read_byte(unsigned device, unsigned address)
21 return 0xFF; /* No DIMM1, don't even try. */
23 return smbus_read_byte(device, address);
26 #include "northbridge/amd/gx2/raminit.h"
27 #include "northbridge/amd/gx2/pll_reset.c"
28 #include "northbridge/amd/gx2/raminit.c"
29 #include "lib/generic_sdram.c"
30 #include "cpu/amd/model_gx2/cpureginit.c"
31 #include "cpu/amd/model_gx2/syspreinit.c"
32 #include "cpu/amd/model_lx/msrinit.c"
34 void main(unsigned long bist)
36 static const struct mem_controller memctrl [] = {
37 {.channel0 = {DIMM0, DIMM1}}
42 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
48 /* Halt if there was a built in self test failure */
49 report_bist_failure(bist);
54 print_err("done cpuRegInit\n");
56 sdram_initialize(1, memctrl);