src/mainboard/amd/rumba/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/hlt.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
  13 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  14 #include "cpu/x86/bist.h"
  15 #include "cpu/x86/msr.h"
  16
  17 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  18
  19 //#include "lib/delay.c"
  20 #include "northbridge/amd/gx2/raminit.h"
  21 #include "northbridge/amd/gx2/raminit.c"
  22 #include "sdram/generic_sdram.c"
  23
  24 static void msr_init(void)
  25 {
  26
  27         __builtin_wrmsr(0x1808, 0x22fffc02, 0x10f3bf00);
  28
  29         __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
  30         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
  31         __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
  32         __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
  33         __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
  34         __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
  35         __builtin_wrmsr(0x10000080, 0x3, 0x0);
  36
  37         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
  38         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
  39         __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
  40         __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
  41         __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
  42         __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
  43
  44         __builtin_wrmsr(0x400000e3, 0xf0309c10, 0x0);
  45
  46         __builtin_wrmsr(0xc0002001, 0x86002, 0x0);
  47         __builtin_wrmsr(0x80002001, 0x86002, 0x0);
  48         __builtin_wrmsr(0xa0002001, 0x86002, 0x0);
  49         __builtin_wrmsr(0x50002001, 0x27, 0x0);
  50         __builtin_wrmsr(0x4c002001, 0x1, 0x0);
  51
  52         __builtin_wrmsr(0x20000018, 0x3400, 0x10076013);
  53         __builtin_wrmsr(0x20000019, 0x696332a3, 0x18000008);
  54         __builtin_wrmsr(0x2000001a, 0x101, 0x0);
  55
  56         __builtin_wrmsr(0x2000001c, 0xff00ff, 0x0);
  57         __builtin_wrmsr(0x2000001d, 0x0, 0x0);
  58         __builtin_wrmsr(0x2000001f, 0x0, 0x0);
  59         __builtin_wrmsr(0x20000020, 0x6, 0x0);
  60
  61 }
  62
  63 static pll_reset(void)
  64 {
  65
  66 }
  67 static void main(unsigned long bist)
  68 {
  69         static const struct mem_controller memctrl [] = {
  70                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
  71         };
  72
  73         msr_init();
  74
  75         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
  76         uart_init();
  77         console_init();
  78
  79         print_err("hi\n");
  80
  81         /* Halt if there was a built in self test failure */
  82         //report_bist_failure(bist);
  83
  84         sdram_initialize(1, memctrl);
  85
  86         /* Check all of memory */
  87         ram_check(0x00000000, 1024*1024);
  88
  89 #if 0
  90         ram_check(0x00000000, msr.lo);
  91
  92         static const struct {
  93                 unsigned long lo, hi;
  94         } check_addrs[] = {
  95                 /* Check 16MB of memory @ 0*/
  96                 { 0x00000000, 0x01000000 },
  97 #if TOTAL_CPUS > 1
  98                 /* Check 16MB of memory @ 2GB */
  99                 { 0x80000000, 0x81000000 },
 100 #endif
 101         };
 102         int i;
 103         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 104                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 105         }
 106 #endif
 107 }