src/mainboard/amd/rumba/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/hlt.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  13 #include "cpu/x86/bist.h"
  14 #include "cpu/x86/msr.h"
  15 #include <cpu/amd/gx2def.h>
  16
  17 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  18
  19 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
  20 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
  21
  22 static inline int spd_read_byte(unsigned device, unsigned address)
  23 {
  24         return smbus_read_byte(device, address);
  25 }
  26
  27 #include "northbridge/amd/gx2/raminit.h"
  28
  29 static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
  30         msr_t msr;
  31         /* 1. Initialize GLMC registers base on SPD values,
  32          * Hard coded as XpressROM for now */
  33         //print_debug("sdram_enable step 1\r\n");
  34         msr = rdmsr(0x20000018);
  35         msr.hi = 0x10076013;
  36         msr.lo = 0x00003000;
  37         wrmsr(0x20000018, msr);
  38
  39         msr = rdmsr(0x20000019);
  40         msr.hi = 0x18000108;
  41         msr.lo = 0x696332a3;
  42         wrmsr(0x20000019, msr);
  43 }
  44
  45 #include "northbridge/amd/gx2/raminit.c"
  46 #include "sdram/generic_sdram.c"
  47
  48 #define PLLMSRhi 0x00001490
  49 #define PLLMSRlo 0x02000030
  50 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
  51 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
  52 #include "northbridge/amd/gx2/pll_reset.c"
  53
  54 static void msr_init(void)
  55 {
  56         __builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
  57
  58         __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
  59         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
  60         __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
  61         __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
  62         __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
  63         __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
  64
  65         __builtin_wrmsr(0x10000080, 0x3, 0x0);
  66
  67         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
  68         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
  69         __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
  70         __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
  71         __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
  72         __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
  73
  74
  75         __builtin_wrmsr(0x50002001, 0x27, 0x0);
  76         __builtin_wrmsr(0x4c002001, 0x1, 0x0);
  77 }
  78
  79
  80 static void main(unsigned long bist)
  81 {
  82         static const struct mem_controller memctrl [] = {
  83                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
  84         };
  85
  86         msr_init();
  87
  88         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
  89         uart_init();
  90         console_init();
  91
  92         cs5535_early_setup();
  93
  94         pll_reset();
  95
  96         /* Halt if there was a built in self test failure */
  97         //report_bist_failure(bist);
  98
  99         sdram_initialize(1, memctrl);
 100
 101
 102         /* Check all of memory */
 103         ram_check(0x00000000, 640*1024);
 104
 105 }