2 #define RC0 ((1<<0)<<8)
3 #define RC1 ((1<<1)<<8)
4 #define RC2 ((1<<2)<<8)
5 #define RC3 ((1<<3)<<8)
13 static inline void activate_spd_rom(const struct mem_controller *ctrl)
20 * This function is dedicated to Daniele Frijia <realcosmo@spd-online.de>
23 static int spd_read_byte(unsigned device, unsigned address)
25 static const unsigned char infinion_512mb_pc2700[0x80] = {
26 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00,
27 0x04, 0x60, 0x70, 0x02, 0x82, 0x04, 0x04, 0x01,
28 0x0e, 0x04, 0x0c, 0x01, 0x02, 0x26, 0xc0, 0x75,
29 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x80,
30 0x75, 0x75, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
31 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x00,
32 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
33 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47,
34 0xc1, 0x49, 0x4e, 0x46, 0x49, 0x4e, 0x45, 0x4f,
35 0x53, 0x37, 0x32, 0x44, 0x36, 0x34, 0x33, 0x30,
36 0x30, 0x47, 0x42, 0x52, 0x36, 0x42, 0x20, 0x20,
37 0x20, 0x20, 0x20, 0x02, 0x0a, 0x03, 0x21, 0x0d,
38 0x3d, 0x89, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00,
39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
40 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
41 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
47 /* This code is AMD quartet specific.
48 * DIMM0 and DIMM1 are defines of the original smbus device
49 * numbers on the quartet. We read them here to see which
50 * spd rom we should fake.
51 * Below construct assumes that the first two dimm sockets
52 * of each cpu hold a 512MB Infinion PC2700 CL2.5 ECC registered
57 if (device == DIMM0 || device == DIMM1) {
58 return infinion_512mb_pc2700[address];