src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 #define MAXIMUM_CONSOLE_LOGLEVEL 9
   3 #define DEFAULT_CONSOLE_LOGLEVEL 9
   4
   5 #include <stdint.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <arch/smp/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/k8/apic_timer.c"
  20 #include "lib/delay.c"
  21 #include "cpu/p6/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "northbridge/amd/amdk8/cpu_rev.c"
  25 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         set_bios_reset();
  32         /* enable cf9 */
  33         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  34         /* reset */
  35         outb(0x0e, 0x0cf9);
  36 }
  37
  38 static void soft_reset(void)
  39 {
  40         set_bios_reset();
  41         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  42 }
  43
  44
  45 static void memreset_setup(void)
  46 {
  47         if (is_cpu_pre_c0()) {
  48                 /* Set the memreset low */
  49                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  50                 /* Ensure the BIOS has control of the memory lines */
  51                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  52         }
  53         else {
  54                 /* Ensure the CPU has controll of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  56         }
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61         if (is_cpu_pre_c0()) {
  62                 udelay(800);
  63                 /* Set memreset_high */
  64                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  65                 udelay(90);
  66         }
  67 }
  68
  69 /*
  70  * generate_row is specific to board implementation
  71  *
  72  */
  73
  74 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  75 {
  76         /* Routing Table Node i
  77          *
  78          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  79          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  80          *
  81          * [ 0: 3] Request Route
  82          *     [0] Route to this node
  83          *     [1] Route to Link 0
  84          *     [2] Route to Link 1
  85          *     [3] Route to Link 2
  86          * [11: 8] Response Route
  87          *     [0] Route to this node
  88          *     [1] Route to Link 0
  89          *     [2] Route to Link 1
  90          *     [3] Route to Link 2
  91          * [19:16] Broadcast route
  92          *     [0] Route to this node
  93          *     [1] Route to Link 0
  94          *     [2] Route to Link 1
  95          *     [3] Route to Link 2
  96          */
  97
  98         uint32_t ret=0x00010101; /* default row entry */
  99
 100         static const unsigned int rows_2p[2][2] = {
 101                 { 0x00030101, 0x00010202 },
 102                 { 0x00010202, 0x00030101 }
 103         };
 104
 105         static const unsigned int rows_4p[4][4] = {
 106                 { 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
 107                 { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
 108                 { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
 109                 { 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
 110         };
 111
 112         if (!(node>=maxnodes || row>=maxnodes)) {
 113                 if (maxnodes==2)
 114                         ret=rows_2p[node][row];
 115                 if (maxnodes==4)
 116                         ret=rows_4p[node][row];
 117         }
 118
 119         return ret;
 120 }
 121
 122
 123 #if ( FAKE_SPDROM != 1 )
 124 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 125 {
 126 #define SMBUS_HUB 0x18
 127         unsigned device=(ctrl->channel0[0])>>8;
 128         smbus_write_byte(SMBUS_HUB , 0x01, device);
 129         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 130 }
 131
 132 static inline int spd_read_byte(unsigned device, unsigned address)
 133 {
 134         return smbus_read_byte(device & 0xff, address);
 135 }
 136 #else
 137 #include "fakespd.c"
 138 #endif
 139
 140 /* no specific code here. this should go away completely */
 141 static void coherent_ht_mainboard(unsigned cpus)
 142 {
 143 }
 144
 145 #include "northbridge/amd/amdk8/raminit.c"
 146
 147 #define CONNECTION_0_1 UP
 148 #define CONNECTION_0_2 ACROSS
 149 #define CONNECTION_1_3 DOWN
 150
 151 #include "northbridge/amd/amdk8/coherent_ht.c"
 152 #include "sdram/generic_sdram.c"
 153
 154 #include "resourcemap.c" /* quartet does not want the default */
 155
 156 #define RC0 ((1<<1)<<8)
 157 #define RC1 ((1<<2)<<8)
 158 #define RC2 ((1<<3)<<8)
 159 #define RC3 ((1<<4)<<8)
 160
 161 #define DIMM0 0x50
 162 #define DIMM1 0x51
 163 #define DIMM2 0x52
 164 #define DIMM3 0x53
 165
 166 static void main(void)
 167 {
 168         static const struct mem_controller cpu[] = {
 169                 {
 170                         .node_id = 0,
 171                         .f0 = PCI_DEV(0, 0x18, 0),
 172                         .f1 = PCI_DEV(0, 0x18, 1),
 173                         .f2 = PCI_DEV(0, 0x18, 2),
 174                         .f3 = PCI_DEV(0, 0x18, 3),
 175                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 176                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 177                 },
 178                 {
 179                         .node_id = 1,
 180                         .f0 = PCI_DEV(0, 0x19, 0),
 181                         .f1 = PCI_DEV(0, 0x19, 1),
 182                         .f2 = PCI_DEV(0, 0x19, 2),
 183                         .f3 = PCI_DEV(0, 0x19, 3),
 184                         .channel0 = { RC1|DIMM0, RC1|DIMM2, 0, 0 },
 185                         .channel1 = { RC1|DIMM1, RC1|DIMM3, 0, 0 },
 186                 },
 187                 {
 188                         .node_id = 2,
 189                         .f0 = PCI_DEV(0, 0x1a, 0),
 190                         .f1 = PCI_DEV(0, 0x1a, 1),
 191                         .f2 = PCI_DEV(0, 0x1a, 2),
 192                         .f3 = PCI_DEV(0, 0x1a, 3),
 193                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 194                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 195                 },
 196                 {
 197                         .node_id = 3,
 198                         .f0 = PCI_DEV(0, 0x1b, 0),
 199                         .f1 = PCI_DEV(0, 0x1b, 1),
 200                         .f2 = PCI_DEV(0, 0x1b, 2),
 201                         .f3 = PCI_DEV(0, 0x1b, 3),
 202                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 203                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 204                 }
 205         };
 206         int needs_reset;
 207
 208         enable_lapic();
 209         init_timer();
 210
 211         if (cpu_init_detected()) {
 212                 asm("jmp __cpu_reset");
 213         }
 214
 215         distinguish_cpu_resets();
 216
 217         if (!boot_cpu()) {
 218                 stop_this_cpu();
 219         }
 220
 221         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 222         uart_init();
 223         console_init();
 224         setup_quartet_resource_map();
 225         needs_reset = setup_coherent_ht_domain();
 226         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 227         if (needs_reset) {
 228                 print_info("ht reset -");
 229                 soft_reset();
 230         }
 231 #if 0
 232         print_pci_devices();
 233 #endif
 234         enable_smbus();
 235 #if 0
 236         dump_spd_registers(&cpu[0]);
 237 #endif
 238         memreset_setup();
 239         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 240
 241 #if 0
 242         dump_pci_devices();
 243 #endif
 244 #if 0
 245         dump_pci_device(PCI_DEV(0, 0x18, 2));
 246 #endif
 247 #if 0
 248         /* Check the first 1M */
 249         ram_check(0x00000000, 0x000100000);
 250 #endif
 251 }