src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 #define MAXIMUM_CONSOLE_LOGLEVEL 9
   3 #define DEFAULT_CONSOLE_LOGLEVEL 9
   4
   5 #include <stdint.h>
   6 #include <device/pci_def.h>
   7 #include <cpu/p6/apic.h>
   8 #include <arch/io.h>
   9 #include <device/pnp.h>
  10 #include <arch/romcc_io.h>
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "northbridge/amd/amdk8/early_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/k8/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/p6/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "debug.c"
  22
  23 #define SIO_BASE 0x2e
  24
  25 static void memreset_setup(void)
  26 {
  27         /* Set the memreset low */
  28         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  29         /* Ensure the BIOS has control of the memory lines */
  30         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  31         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 30);
  32         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 31);
  33 }
  34
  35 static void memreset(int controllers, const struct mem_controller *ctrl)
  36 {
  37         udelay(800);
  38         /* Set memreset_high */
  39         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  40         udelay(90);
  41 }
  42
  43 /*
  44  * generate_row is specific to board implementation
  45  *
  46  */
  47
  48 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  49 {
  50         /* Routing Table Node i
  51          *
  52          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  53          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  54          *
  55          * [ 0: 3] Request Route
  56          *     [0] Route to this node
  57          *     [1] Route to Link 0
  58          *     [2] Route to Link 1
  59          *     [3] Route to Link 2
  60          * [11: 8] Response Route
  61          *     [0] Route to this node
  62          *     [1] Route to Link 0
  63          *     [2] Route to Link 1
  64          *     [3] Route to Link 2
  65          * [19:16] Broadcast route
  66          *     [0] Route to this node
  67          *     [1] Route to Link 0
  68          *     [2] Route to Link 1
  69          *     [3] Route to Link 2
  70          */
  71
  72         uint32_t ret=0x00010101; /* default row entry */
  73
  74         static const unsigned int rows_2p[2][2] = {
  75                 { 0x00030101, 0x00010202 },
  76                 { 0x00010202, 0x00030101 }
  77         };
  78
  79         static const unsigned int rows_4p[4][4] = {
  80                 { 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
  81                 { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
  82                 { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
  83                 { 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
  84         };
  85
  86         if (!(node>=maxnodes || row>=maxnodes)) {
  87                 if (maxnodes==2)
  88                         ret=rows_2p[node][row];
  89                 if (maxnodes==4)
  90                         ret=rows_4p[node][row];
  91         }
  92
  93         return ret;
  94 }
  95
  96 static inline int spd_read_byte(unsigned device, unsigned address)
  97 {
  98 #define SMBUS_HUB 0x30
  99         unsigned hub = device >> 8;
 100
 101         device &= 0xff;
 102         // smbus_write_byte(SMBUS_HUB, hub);
 103         return smbus_read_byte(device, address);
 104
 105 }
 106
 107 /* no specific code here. this should go away completely */
 108 static void coherent_ht_mainboard(unsigned cpus)
 109 {
 110 }
 111
 112 #include "northbridge/amd/amdk8/cpu_ldtstop.c"
 113 #include "southbridge/amd/amd8111/amd8111_ldtstop.c"
 114
 115 #include "northbridge/amd/amdk8/raminit.c"
 116
 117 #define CONNECTION_0_1 UP
 118 #define CONNECTION_0_2 ACROSS
 119 #define CONNECTION_1_3 DOWN
 120
 121 #include "northbridge/amd/amdk8/coherent_ht.c"
 122 #include "sdram/generic_sdram.c"
 123
 124 #include "resourcemap.c" /* quartet does not want the default */
 125
 126 static void enable_lapic(void)
 127 {
 128
 129         msr_t msr;
 130         msr = rdmsr(0x1b);
 131         msr.hi &= 0xffffff00;
 132         msr.lo &= 0x000007ff;
 133         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
 134         wrmsr(0x1b, msr);
 135 }
 136
 137 static void stop_this_cpu(void)
 138 {
 139         unsigned apicid;
 140         apicid = apic_read(APIC_ID) >> 24;
 141
 142         /* Send an APIC INIT to myself */
 143         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 144         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 145         /* Wait for the ipi send to finish */
 146         apic_wait_icr_idle();
 147
 148         /* Deassert the APIC INIT */
 149         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 150         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 151         /* Wait for the ipi send to finish */
 152         apic_wait_icr_idle();
 153
 154         /* If I haven't halted spin forever */
 155         for(;;) {
 156                 hlt();
 157         }
 158 }
 159
 160 #define PC87360_FDC  0x00
 161 #define PC87360_PP   0x01
 162 #define PC87360_SP2  0x02
 163 #define PC87360_SP1  0x03
 164 #define PC87360_SWC  0x04
 165 #define PC87360_KBCM 0x05
 166 #define PC87360_KBCK 0x06
 167 #define PC87360_GPIO 0x07
 168 #define PC87360_ACB  0x08
 169 #define PC87360_FSCM 0x09
 170 #define PC87360_WDT  0x0A
 171
 172 static void pc87360_enable_serial(void)
 173 {
 174         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 175         pnp_set_enable(SIO_BASE, 1);
 176         pnp_set_iobase0(SIO_BASE, 0x3f8);
 177 }
 178
 179 #define RC0 (0<<8)
 180 #define RC1 (1<<8)
 181 #define RC2 (2<<8)
 182 #define RC3 (3<<8)
 183
 184 #define DIMM0 0xa0
 185 #define DIMM1 0xa2
 186 #define DIMM2 0xa4
 187 #define DIMM3 0xa8
 188
 189 static void main(void)
 190 {
 191         static const struct mem_controller cpu[] = {
 192                 {
 193                         .node_id = 0,
 194                         .f0 = PCI_DEV(0, 0x18, 0),
 195                         .f1 = PCI_DEV(0, 0x18, 1),
 196                         .f2 = PCI_DEV(0, 0x18, 2),
 197                         .f3 = PCI_DEV(0, 0x18, 3),
 198                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 199                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 200                 },
 201                 {
 202                         .node_id = 1,
 203                         .f0 = PCI_DEV(0, 0x19, 0),
 204                         .f1 = PCI_DEV(0, 0x19, 1),
 205                         .f2 = PCI_DEV(0, 0x19, 2),
 206                         .f3 = PCI_DEV(0, 0x19, 3),
 207                         .channel0 = { RC1|DIMM0, RC1|DIMM2, 0, 0 },
 208                         .channel1 = { RC1|DIMM1, RC1|DIMM3, 0, 0 },
 209                 },
 210                 {
 211                         .node_id = 2,
 212                         .f0 = PCI_DEV(0, 0x1a, 0),
 213                         .f1 = PCI_DEV(0, 0x1a, 1),
 214                         .f2 = PCI_DEV(0, 0x1a, 2),
 215                         .f3 = PCI_DEV(0, 0x1a, 3),
 216                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 217                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 218                 },
 219                 {
 220                         .node_id = 3,
 221                         .f0 = PCI_DEV(0, 0x1b, 0),
 222                         .f1 = PCI_DEV(0, 0x1b, 1),
 223                         .f2 = PCI_DEV(0, 0x1b, 2),
 224                         .f3 = PCI_DEV(0, 0x1b, 3),
 225                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 226                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 227                 }
 228         };
 229         if (cpu_init_detected()) {
 230                 asm("jmp __cpu_reset");
 231         }
 232         enable_lapic();
 233         init_timer();
 234         if (!boot_cpu()) {
 235 //              notify_bsp_ap_is_stopped();
 236                 stop_this_cpu();
 237         }
 238         pc87360_enable_serial();
 239         uart_init();
 240         console_init();
 241         setup_quartet_resource_map();
 242         setup_coherent_ht_domain();
 243         enumerate_ht_chain(0);
 244         distinguish_cpu_resets(0);
 245
 246 #if 0
 247         print_pci_devices();
 248 #endif
 249         enable_smbus();
 250 #if 0
 251         dump_spd_registers(&cpu[0]);
 252 #endif
 253         memreset_setup();
 254         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 255
 256 #if 0
 257         dump_pci_devices();
 258 #endif
 259 #if 0
 260         dump_pci_device(PCI_DEV(0, 0x18, 2));
 261 #endif
 262
 263         /* Check all of memory */
 264 #if 0
 265         msr_t msr;
 266         msr = rdmsr(TOP_MEM);
 267         print_debug("TOP_MEM: ");
 268         print_debug_hex32(msr.hi);
 269         print_debug_hex32(msr.lo);
 270         print_debug("\r\n");
 271 #endif
 272 #if 0
 273         ram_check(0x00000000, msr.lo);
 274 #else
 275         /* Check 16MB of memory */
 276         ram_check(0x00000000, 0x01000000);
 277 #endif
 278 }