src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 #define MAXIMUM_CONSOLE_LOGLEVEL 9
   3 #define DEFAULT_CONSOLE_LOGLEVEL 9
   4
   5 #include <stdint.h>
   6 #include <device/pci_def.h>
   7 #include <cpu/p6/apic.h>
   8 #include <arch/io.h>
   9 #include <device/pnp.h>
  10 #include <arch/romcc_io.h>
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "northbridge/amd/amdk8/early_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/k8/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/p6/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "debug.c"
  22 #include "northbridge/amd/amdk8/cpu_rev.c"
  23
  24 #define SIO_BASE 0x2e
  25
  26 static void memreset_setup(void)
  27 {
  28         if (is_cpu_pre_c0()) {
  29                 /* Set the memreset low */
  30                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  31                 /* Ensure the BIOS has control of the memory lines */
  32                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  33         }
  34         else {
  35                 /* Ensure the CPU has controll of the memory lines */
  36                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  37         }
  38 }
  39
  40 static void memreset(int controllers, const struct mem_controller *ctrl)
  41 {
  42         if (is_cpu_pre_c0()) {
  43                 udelay(800);
  44                 /* Set memreset_high */
  45                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  46                 udelay(90);
  47         }
  48 }
  49
  50 /*
  51  * generate_row is specific to board implementation
  52  *
  53  */
  54
  55 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  56 {
  57         /* Routing Table Node i
  58          *
  59          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  60          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  61          *
  62          * [ 0: 3] Request Route
  63          *     [0] Route to this node
  64          *     [1] Route to Link 0
  65          *     [2] Route to Link 1
  66          *     [3] Route to Link 2
  67          * [11: 8] Response Route
  68          *     [0] Route to this node
  69          *     [1] Route to Link 0
  70          *     [2] Route to Link 1
  71          *     [3] Route to Link 2
  72          * [19:16] Broadcast route
  73          *     [0] Route to this node
  74          *     [1] Route to Link 0
  75          *     [2] Route to Link 1
  76          *     [3] Route to Link 2
  77          */
  78
  79         uint32_t ret=0x00010101; /* default row entry */
  80
  81         static const unsigned int rows_2p[2][2] = {
  82                 { 0x00030101, 0x00010202 },
  83                 { 0x00010202, 0x00030101 }
  84         };
  85
  86         static const unsigned int rows_4p[4][4] = {
  87                 { 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
  88                 { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
  89                 { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
  90                 { 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
  91         };
  92
  93         if (!(node>=maxnodes || row>=maxnodes)) {
  94                 if (maxnodes==2)
  95                         ret=rows_2p[node][row];
  96                 if (maxnodes==4)
  97                         ret=rows_4p[node][row];
  98         }
  99
 100         return ret;
 101 }
 102
 103 static inline int spd_read_byte(unsigned device, unsigned address)
 104 {
 105 #define SMBUS_HUB 0x30
 106         unsigned hub = device >> 8;
 107
 108         device &= 0xff;
 109         smbus_write_byte(SMBUS_HUB, 0x01, 1<<hub);
 110         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 111
 112         return smbus_read_byte(device, address);
 113 }
 114
 115 /* no specific code here. this should go away completely */
 116 static void coherent_ht_mainboard(unsigned cpus)
 117 {
 118 }
 119
 120 #include "northbridge/amd/amdk8/raminit.c"
 121
 122 #define CONNECTION_0_1 UP
 123 #define CONNECTION_0_2 ACROSS
 124 #define CONNECTION_1_3 DOWN
 125
 126 #include "northbridge/amd/amdk8/coherent_ht.c"
 127 #include "sdram/generic_sdram.c"
 128
 129 #include "resourcemap.c" /* quartet does not want the default */
 130
 131 static void enable_lapic(void)
 132 {
 133
 134         msr_t msr;
 135         msr = rdmsr(0x1b);
 136         msr.hi &= 0xffffff00;
 137         msr.lo &= 0x000007ff;
 138         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
 139         wrmsr(0x1b, msr);
 140 }
 141
 142 static void stop_this_cpu(void)
 143 {
 144         unsigned apicid;
 145         apicid = apic_read(APIC_ID) >> 24;
 146
 147         /* Send an APIC INIT to myself */
 148         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 149         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 150         /* Wait for the ipi send to finish */
 151         apic_wait_icr_idle();
 152
 153         /* Deassert the APIC INIT */
 154         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 155         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 156         /* Wait for the ipi send to finish */
 157         apic_wait_icr_idle();
 158
 159         /* If I haven't halted spin forever */
 160         for(;;) {
 161                 hlt();
 162         }
 163 }
 164
 165 #define PC87360_FDC  0x00
 166 #define PC87360_PP   0x01
 167 #define PC87360_SP2  0x02
 168 #define PC87360_SP1  0x03
 169 #define PC87360_SWC  0x04
 170 #define PC87360_KBCM 0x05
 171 #define PC87360_KBCK 0x06
 172 #define PC87360_GPIO 0x07
 173 #define PC87360_ACB  0x08
 174 #define PC87360_FSCM 0x09
 175 #define PC87360_WDT  0x0A
 176
 177 static void pc87360_enable_serial(void)
 178 {
 179         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 180         pnp_set_enable(SIO_BASE, 1);
 181         pnp_set_iobase0(SIO_BASE, 0x3f8);
 182 }
 183
 184 #define RC0 (0<<8)
 185 #define RC1 (1<<8)
 186 #define RC2 (2<<8)
 187 #define RC3 (3<<8)
 188
 189 #define DIMM0 0xa0
 190 #define DIMM1 0xa2
 191 #define DIMM2 0xa4
 192 #define DIMM3 0xa8
 193
 194 static void main(void)
 195 {
 196         static const struct mem_controller cpu[] = {
 197                 {
 198                         .node_id = 0,
 199                         .f0 = PCI_DEV(0, 0x18, 0),
 200                         .f1 = PCI_DEV(0, 0x18, 1),
 201                         .f2 = PCI_DEV(0, 0x18, 2),
 202                         .f3 = PCI_DEV(0, 0x18, 3),
 203                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 204                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 205                 },
 206                 {
 207                         .node_id = 1,
 208                         .f0 = PCI_DEV(0, 0x19, 0),
 209                         .f1 = PCI_DEV(0, 0x19, 1),
 210                         .f2 = PCI_DEV(0, 0x19, 2),
 211                         .f3 = PCI_DEV(0, 0x19, 3),
 212                         .channel0 = { RC1|DIMM0, RC1|DIMM2, 0, 0 },
 213                         .channel1 = { RC1|DIMM1, RC1|DIMM3, 0, 0 },
 214                 },
 215                 {
 216                         .node_id = 2,
 217                         .f0 = PCI_DEV(0, 0x1a, 0),
 218                         .f1 = PCI_DEV(0, 0x1a, 1),
 219                         .f2 = PCI_DEV(0, 0x1a, 2),
 220                         .f3 = PCI_DEV(0, 0x1a, 3),
 221                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 222                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 223                 },
 224                 {
 225                         .node_id = 3,
 226                         .f0 = PCI_DEV(0, 0x1b, 0),
 227                         .f1 = PCI_DEV(0, 0x1b, 1),
 228                         .f2 = PCI_DEV(0, 0x1b, 2),
 229                         .f3 = PCI_DEV(0, 0x1b, 3),
 230                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 231                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 232                 }
 233         };
 234         if (cpu_init_detected()) {
 235                 asm("jmp __cpu_reset");
 236         }
 237         enable_lapic();
 238         init_timer();
 239         if (!boot_cpu()) {
 240 //              notify_bsp_ap_is_stopped();
 241                 stop_this_cpu();
 242         }
 243         pc87360_enable_serial();
 244         uart_init();
 245         console_init();
 246         setup_quartet_resource_map();
 247         setup_coherent_ht_domain();
 248         enumerate_ht_chain(0);
 249         distinguish_cpu_resets(0);
 250
 251 #if 0
 252         print_pci_devices();
 253 #endif
 254         enable_smbus();
 255 #if 0
 256         dump_spd_registers(&cpu[0]);
 257 #endif
 258         memreset_setup();
 259         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 260
 261 #if 0
 262         dump_pci_devices();
 263 #endif
 264 #if 0
 265         dump_pci_device(PCI_DEV(0, 0x18, 2));
 266 #endif
 267
 268         /* Check all of memory */
 269 #if 0
 270         msr_t msr;
 271         msr = rdmsr(TOP_MEM);
 272         print_debug("TOP_MEM: ");
 273         print_debug_hex32(msr.hi);
 274         print_debug_hex32(msr.lo);
 275         print_debug("\r\n");
 276 #endif
 277 #if 0
 278         ram_check(0x00000000, msr.lo);
 279 #endif
 280 #if 0
 281         static const struct {
 282                 unsigned long lo, hi;
 283         } check_addrs[] = {
 284                 /* Check 16MB of memory @ 0*/
 285                 { 0x00000000, 0x01000000 },
 286 #if 0
 287                 /* Check 16MB of memory @ 2GB */
 288                 { 0x80000000, 0x81000000 },
 289 #endif
 290         };
 291         int i;
 292         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 293                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 294         }
 295 #endif
 296 }