src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <device/pnp.h>
   7 #include <arch/romcc_io.h>
   8 #include "pc80/serial.c"
   9 #include "arch/i386/lib/console.c"
  10 #include "ram/ramtest.c"
  11 #include "northbridge/amd/amdk8/early_ht.c"
  12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/k8/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "cpu/p6/boot_cpu.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "debug.c"
  19
  20 static void memreset_setup(const struct mem_controller *ctrl)
  21 {
  22         /* Set the memreset low */
  23         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  24         /* Ensure the BIOS has control of the memory lines */
  25         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  26 }
  27
  28 static void memreset(const struct mem_controller *ctrl)
  29 {
  30         udelay(800);
  31         /* Set memreset_high */
  32         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  33         udelay(50);
  34 }
  35
  36 /*
  37  * generate_row is specific to board implementation
  38  *
  39  */
  40
  41 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  42 {
  43         /* Routing Table Node i
  44          *
  45          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  46          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  47          *
  48          * [ 0: 3] Request Route
  49          *     [0] Route to this node
  50          *     [1] Route to Link 0
  51          *     [2] Route to Link 1
  52          *     [3] Route to Link 2
  53          * [11: 8] Response Route
  54          *     [0] Route to this node
  55          *     [1] Route to Link 0
  56          *     [2] Route to Link 1
  57          *     [3] Route to Link 2
  58          * [19:16] Broadcast route
  59          *     [0] Route to this node
  60          *     [1] Route to Link 0
  61          *     [2] Route to Link 1
  62          *     [3] Route to Link 2
  63          */
  64
  65         uint32_t ret=0x00010101; /* default row entry */
  66
  67         static const unsigned int rows_2p[2][2] = {
  68                 { 0x00030101, 0x00010202 },
  69                 { 0x00010202, 0x00030101 }
  70         };
  71
  72         static const unsigned int rows_4p[4][4] = {
  73                 { 0x00070101, 0x00010404, 0x00050202, 0x00010402 },
  74                 { 0x00010808, 0x000b0101, 0x00010802, 0x00090202 },
  75                 { 0x00090202, 0x00010802, 0x000b0101, 0x00010808 },
  76                 { 0x00010402, 0x00050202, 0x00010404, 0x00070101 }
  77         };
  78
  79         if (!(node>=maxnodes || row>=maxnodes)) {
  80                 if (maxnodes==2)
  81                         ret=rows_2p[node][row];
  82                 if (maxnodes==4)
  83                         ret=rows_4p[node][row];
  84         }
  85
  86         return ret;
  87 }
  88
  89 #include "northbridge/amd/amdk8/cpu_ldtstop.c"
  90 #include "southbridge/amd/amd8111/amd8111_ldtstop.c"
  91
  92 #include "northbridge/amd/amdk8/raminit.c"
  93 #include "northbridge/amd/amdk8/coherent_ht.c"
  94 #include "sdram/generic_sdram.c"
  95
  96 #include "resourcemap.c" /* quartet does not want the default */
  97
  98 static void enable_lapic(void)
  99 {
 100
 101         msr_t msr;
 102         msr = rdmsr(0x1b);
 103         msr.hi &= 0xffffff00;
 104         msr.lo &= 0x000007ff;
 105         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
 106         wrmsr(0x1b, msr);
 107 }
 108
 109 static void stop_this_cpu(void)
 110 {
 111         unsigned apicid;
 112         apicid = apic_read(APIC_ID) >> 24;
 113
 114         /* Send an APIC INIT to myself */
 115         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 116         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 117         /* Wait for the ipi send to finish */
 118         apic_wait_icr_idle();
 119
 120         /* Deassert the APIC INIT */
 121         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 122         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 123         /* Wait for the ipi send to finish */
 124         apic_wait_icr_idle();
 125
 126         /* If I haven't halted spin forever */
 127         for(;;) {
 128                 hlt();
 129         }
 130 }
 131
 132 #define PC87360_FDC  0x00
 133 #define PC87360_PP   0x01
 134 #define PC87360_SP2  0x02
 135 #define PC87360_SP1  0x03
 136 #define PC87360_SWC  0x04
 137 #define PC87360_KBCM 0x05
 138 #define PC87360_KBCK 0x06
 139 #define PC87360_GPIO 0x07
 140 #define PC87360_ACB  0x08
 141 #define PC87360_FSCM 0x09
 142 #define PC87360_WDT  0x0A
 143
 144 static void pc87360_enable_serial(void)
 145 {
 146         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 147         pnp_set_enable(SIO_BASE, 1);
 148         pnp_set_iobase0(SIO_BASE, 0x3f8);
 149 }
 150
 151 static void main(void)
 152 {
 153         /*
 154          * GPIO28 of 8111 will control H0_MEMRESET_L
 155          * GPIO29 of 8111 will control H1_MEMRESET_L
 156          */
 157
 158         static const struct mem_controller cpu0 = {
 159                 .f0 = PCI_DEV(0, 0x18, 0),
 160                 .f1 = PCI_DEV(0, 0x18, 1),
 161                 .f2 = PCI_DEV(0, 0x18, 2),
 162                 .f3 = PCI_DEV(0, 0x18, 3),
 163                 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 164                 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 165         };
 166         static const struct mem_controller cpu1 = {
 167                 .f0 = PCI_DEV(0, 0x19, 0),
 168                 .f1 = PCI_DEV(0, 0x19, 1),
 169                 .f2 = PCI_DEV(0, 0x19, 2),
 170                 .f3 = PCI_DEV(0, 0x19, 3),
 171                 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 172                 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 173         };
 174         static const struct mem_controller cpu2 = {
 175                 .f0 = PCI_DEV(0, 0x1a, 0),
 176                 .f1 = PCI_DEV(0, 0x1a, 1),
 177                 .f2 = PCI_DEV(0, 0x1a, 2),
 178                 .f3 = PCI_DEV(0, 0x1a, 3),
 179                 .channel0 = { (0xa<<3)|8, (0xa<<3)|10, 0, 0 },
 180                 .channel1 = { (0xa<<3)|9, (0xa<<3)|11, 0, 0 },
 181         };
 182         static const struct mem_controller cpu3 = {
 183                 .f0 = PCI_DEV(0, 0x1b, 0),
 184                 .f1 = PCI_DEV(0, 0x1b, 1),
 185                 .f2 = PCI_DEV(0, 0x1b, 2),
 186                 .f3 = PCI_DEV(0, 0x1b, 3),
 187                 .channel0 = { (0xa<<3)|12, (0xa<<3)|14, 0, 0 },
 188                 .channel1 = { (0xa<<3)|13, (0xa<<3)|15, 0, 0 },
 189         };
 190
 191         if (cpu_init_detected()) {
 192                 asm("jmp __cpu_reset");
 193         }
 194         pc87360_enable_serial();
 195         uart_init();
 196         console_init();
 197         enable_lapic();
 198         if (!boot_cpu()) {
 199                 stop_this_cpu();
 200         }
 201         init_timer();
 202         setup_default_resource_map();
 203         setup_coherent_ht_domain();
 204         enumerate_ht_chain(0);
 205         distinguish_cpu_resets();
 206
 207 #if 1
 208         print_pci_devices();
 209 #endif
 210         enable_smbus();
 211 #if 0
 212         dump_spd_registers(&cpu0);
 213 #endif
 214         sdram_initialize(&cpu0);
 215
 216 #if 1
 217         dump_pci_devices();
 218 #endif
 219 #if 0
 220         dump_pci_device(PCI_DEV(0, 0x18, 2));
 221 #endif
 222
 223         /* Check all of memory */
 224 #if 0
 225         msr_t msr;
 226         msr = rdmsr(TOP_MEM);
 227         print_debug("TOP_MEM: ");
 228         print_debug_hex32(msr.hi);
 229         print_debug_hex32(msr.lo);
 230         print_debug("\r\n");
 231 #endif
 232 #if 0
 233         ram_check(0x00000000, msr.lo);
 234 #else
 235         /* Check 16MB of memory */
 236         ram_check(0x00000000, 0x01000000);
 237 #endif
 238 }