src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 //#define MAXIMUM_CONSOLE_LOGLEVEL 9
   3 //#define DEFAULT_CONSOLE_LOGLEVEL 9
   4
   5 #include <stdint.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <arch/cpu.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "ram/ramtest.c"
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "northbridge/amd/amdk8/cpu_rev.c"
  26 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  27 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  31
  32 static void hard_reset(void)
  33 {
  34         set_bios_reset();
  35         /* enable cf9 */
  36         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  37         /* reset */
  38         outb(0x0e, 0x0cf9);
  39 }
  40
  41 static void soft_reset(void)
  42 {
  43         set_bios_reset();
  44         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  45 }
  46
  47 /*
  48  * GPIO28 of 8111 will control H0_MEMRESET_L
  49  * GPIO29 of 8111 will control H1_MEMRESET_L
  50  */
  51 static void memreset_setup(void)
  52 {
  53         if (is_cpu_pre_c0()) {
  54                 /* Set the memreset low */
  55                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  56                      (0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
  57                 /* Ensure the BIOS has control of the memory lines */
  58                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  59                      (0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
  60         } else {
  61                 /* Ensure the CPU has controll of the memory lines */
  62                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  63                      (1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
  64         }
  65 }
  66
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69         if (is_cpu_pre_c0()) {
  70                 udelay(800);
  71                 /* Set memreset_high */
  72                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  73                      (1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
  74                 udelay(90);
  75         }
  76 }
  77
  78 /*
  79  * generate_row is specific to board implementation
  80  *
  81  */
  82
  83 static unsigned int generate_row(uint8_t node, uint8_t row,
  84                                  uint8_t maxnodes)
  85 {
  86         /* Routing Table Node i
  87          *
  88          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  89          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  90          *
  91          * [ 0: 3] Request Route
  92          *     [0] Route to this node
  93          *     [1] Route to Link 0
  94          *     [2] Route to Link 1
  95          *     [3] Route to Link 2
  96          * [11: 8] Response Route
  97          *     [0] Route to this node
  98          *     [1] Route to Link 0
  99          *     [2] Route to Link 1
 100          *     [3] Route to Link 2
 101          * [19:16] Broadcast route
 102          *     [0] Route to this node
 103          *     [1] Route to Link 0
 104          *     [2] Route to Link 1
 105          *     [3] Route to Link 2
 106          */
 107
 108         uint32_t ret = 0x00010101;      /* default row entry */
 109 /*
 110         static const unsigned int rows_2p[2][2] = {
 111                 {0x00030101, 0x00010202},
 112                 {0x00010202, 0x00030101}
 113         };
 114 */
 115
 116         static const unsigned int rows_4p[4][4] = {
 117                 {0x00070101, 0x00010202, 0x00030404, 0x00010204},
 118                 {0x00010202, 0x000b0101, 0x00010208, 0x00030808},
 119                 {0x00030808, 0x00010208, 0x000b0101, 0x00010202},
 120                 {0x00010204, 0x00030404, 0x00010202, 0x00070101}
 121         };
 122
 123         if (!(node >= maxnodes || row >= maxnodes)) {
 124 /*
 125                 if (maxnodes == 2)
 126                         ret = rows_2p[node][row];
 127                 if (maxnodes == 4)
 128 */
 129                         ret = rows_4p[node][row];
 130         }
 131
 132         return ret;
 133 }
 134
 135
 136 #if ( FAKE_SPDROM != 1 )
 137 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 138 {
 139 #define SMBUS_HUB 0x18
 140         unsigned device = (ctrl->channel0[0]) >> 8;
 141         smbus_write_byte(SMBUS_HUB, 0x01, device);
 142         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 143 }
 144
 145 static inline int spd_read_byte(unsigned device, unsigned address)
 146 {
 147         return smbus_read_byte(device & 0xff, address);
 148 }
 149 #else
 150 #include "fakespd.c"
 151 #endif
 152
 153 // #include "northbridge/amd/amdk8/setup_resource_map.c"
 154 #include "northbridge/amd/amdk8/raminit.c"
 155 #include "northbridge/amd/amdk8/coherent_ht.c"
 156 #include "sdram/generic_sdram.c"
 157 /* quartet does not want the default */
 158 #include "resourcemap.c"
 159
 160 #define RC0 ((1<<1)<<8)
 161 #define RC1 ((1<<2)<<8)
 162 #define RC2 ((1<<3)<<8)
 163 #define RC3 ((1<<4)<<8)
 164
 165 #define DIMM0 0x50
 166 #define DIMM1 0x51
 167 #define DIMM2 0x52
 168 #define DIMM3 0x53
 169
 170 static void main(unsigned long bist)
 171 {
 172         static const struct mem_controller cpu[] = {
 173                 {
 174                  .node_id = 0,
 175                  .f0 = PCI_DEV(0, 0x18, 0),
 176                  .f1 = PCI_DEV(0, 0x18, 1),
 177                  .f2 = PCI_DEV(0, 0x18, 2),
 178                  .f3 = PCI_DEV(0, 0x18, 3),
 179                  .channel0 = {RC0 | DIMM0, RC0 | DIMM2, 0, 0},
 180                  .channel1 = {RC0 | DIMM1, RC0 | DIMM3, 0, 0},
 181                  },
 182                 {
 183                  .node_id = 1,
 184                  .f0 = PCI_DEV(0, 0x19, 0),
 185                  .f1 = PCI_DEV(0, 0x19, 1),
 186                  .f2 = PCI_DEV(0, 0x19, 2),
 187                  .f3 = PCI_DEV(0, 0x19, 3),
 188                  .channel0 = {RC1 | DIMM0, RC1 | DIMM2, 0, 0},
 189                  .channel1 = {RC1 | DIMM1, RC1 | DIMM3, 0, 0},
 190                  },
 191                 {
 192                  .node_id = 2,
 193                  .f0 = PCI_DEV(0, 0x1a, 0),
 194                  .f1 = PCI_DEV(0, 0x1a, 1),
 195                  .f2 = PCI_DEV(0, 0x1a, 2),
 196                  .f3 = PCI_DEV(0, 0x1a, 3),
 197                  .channel0 = {RC2 | DIMM0, RC2 | DIMM2, 0, 0},
 198                  .channel1 = {RC2 | DIMM1, RC2 | DIMM3, 0, 0},
 199                  },
 200                 {
 201                  .node_id = 3,
 202                  .f0 = PCI_DEV(0, 0x1b, 0),
 203                  .f1 = PCI_DEV(0, 0x1b, 1),
 204                  .f2 = PCI_DEV(0, 0x1b, 2),
 205                  .f3 = PCI_DEV(0, 0x1b, 3),
 206                  .channel0 = {RC3 | DIMM0, RC3 | DIMM2, 0, 0},
 207                  .channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0},
 208                  }
 209         };
 210
 211         static const struct ht_chain ht_c[] = {
 212                 {  /* Link 2 of CPU0 */
 213                         .devreg = 0xe0,  /* Preset bus num in resource map */
 214                 },
 215                 {  /* Link 1 of CPU1 */
 216                         .devreg = 0xe4,  /* Preset bus num in resource map */
 217                 },
 218         };
 219
 220         int needs_reset;
 221
 222         if (bist == 0) {
 223                 /* Skip this if there was a built in self test failure */
 224                 amd_early_mtrr_init();
 225                 enable_lapic();
 226                 init_timer();
 227                 /* Has this cpu already booted? */
 228                 if (cpu_init_detected()) {
 229                         asm volatile ("jmp __cpu_reset");
 230                 }
 231
 232                 distinguish_cpu_resets();
 233
 234                 if (!boot_cpu()) {
 235                         stop_this_cpu();
 236                 }
 237         }
 238         /* Setup the console */
 239         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 240         uart_init();
 241         console_init();
 242
 243         /* Halt if there was a built in self test failure */
 244         report_bist_failure(bist);
 245
 246         setup_quartet_resource_map();
 247         needs_reset = setup_coherent_ht_domain();
 248 //      needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 249         needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
 250         if (needs_reset) {
 251                 print_info("ht reset -\r\n");
 252                 soft_reset();
 253         }
 254 #if 0
 255         print_pci_devices();
 256 #endif
 257         enable_smbus();
 258 #if 0
 259         dump_spd_registers(&cpu[0]);
 260 #endif
 261         memreset_setup();
 262         sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
 263
 264 #if 0
 265         dump_pci_devices();
 266 #endif
 267 #if 0
 268         dump_pci_device(PCI_DEV(0, 0x18, 2));
 269 #endif
 270 #if 0
 271         /* Check the first 1M */
 272         ram_check(0x00000000, 0x000100000);
 273 #endif
 274 }