src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 #define MAXIMUM_CONSOLE_LOGLEVEL 9
   3 #define DEFAULT_CONSOLE_LOGLEVEL 9
   4
   5 #include <stdint.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <arch/smp/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/k8/apic_timer.c"
  20 #include "lib/delay.c"
  21 #include "cpu/p6/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "northbridge/amd/amdk8/cpu_rev.c"
  25 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         set_bios_reset();
  32         /* enable cf9 */
  33         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  34         /* reset */
  35         outb(0x0e, 0x0cf9);
  36 }
  37
  38 static void soft_reset(void)
  39 {
  40         set_bios_reset();
  41         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  42 }
  43
  44
  45 static void memreset_setup(void)
  46 {
  47         if (is_cpu_pre_c0()) {
  48                 /* Set the memreset low */
  49                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  50                      (0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
  51                 /* Ensure the BIOS has control of the memory lines */
  52                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  53                      (0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
  54         } else {
  55                 /* Ensure the CPU has controll of the memory lines */
  56                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  57                      (1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
  58         }
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63         if (is_cpu_pre_c0()) {
  64                 udelay(800);
  65                 /* Set memreset_high */
  66                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  67                      (1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
  68                 udelay(90);
  69         }
  70 }
  71
  72 /*
  73  * generate_row is specific to board implementation
  74  *
  75  */
  76
  77 static unsigned int generate_row(uint8_t node, uint8_t row,
  78                                  uint8_t maxnodes)
  79 {
  80         /* Routing Table Node i
  81          *
  82          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  83          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  84          *
  85          * [ 0: 3] Request Route
  86          *     [0] Route to this node
  87          *     [1] Route to Link 0
  88          *     [2] Route to Link 1
  89          *     [3] Route to Link 2
  90          * [11: 8] Response Route
  91          *     [0] Route to this node
  92          *     [1] Route to Link 0
  93          *     [2] Route to Link 1
  94          *     [3] Route to Link 2
  95          * [19:16] Broadcast route
  96          *     [0] Route to this node
  97          *     [1] Route to Link 0
  98          *     [2] Route to Link 1
  99          *     [3] Route to Link 2
 100          */
 101
 102         uint32_t ret = 0x00010101;      /* default row entry */
 103
 104         static const unsigned int rows_2p[2][2] = {
 105                 {0x00030101, 0x00010202},
 106                 {0x00010202, 0x00030101}
 107         };
 108
 109         static const unsigned int rows_4p[4][4] = {
 110                 {0x00070101, 0x00010202, 0x00030404, 0x00010204},
 111                 {0x00010202, 0x000b0101, 0x00010208, 0x00030808},
 112                 {0x00030808, 0x00010208, 0x000b0101, 0x00010202},
 113                 {0x00010204, 0x00030404, 0x00010202, 0x00070101}
 114         };
 115
 116         if (!(node >= maxnodes || row >= maxnodes)) {
 117                 if (maxnodes == 2)
 118                         ret = rows_2p[node][row];
 119                 if (maxnodes == 4)
 120                         ret = rows_4p[node][row];
 121         }
 122
 123         return ret;
 124 }
 125
 126
 127 #if ( FAKE_SPDROM != 1 )
 128 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 129 {
 130 #define SMBUS_HUB 0x18
 131         unsigned device = (ctrl->channel0[0]) >> 8;
 132         smbus_write_byte(SMBUS_HUB, 0x01, device);
 133         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 134 }
 135
 136 static inline int spd_read_byte(unsigned device, unsigned address)
 137 {
 138         return smbus_read_byte(device & 0xff, address);
 139 }
 140 #else
 141 #include "fakespd.c"
 142 #endif
 143
 144 #include "northbridge/amd/amdk8/raminit.c"
 145
 146 #include "northbridge/amd/amdk8/coherent_ht.c"
 147
 148 #include "sdram/generic_sdram.c"
 149
 150 #include "resourcemap.c"        /* quartet does not want the default */
 151
 152 #define RC0 ((1<<1)<<8)
 153 #define RC1 ((1<<2)<<8)
 154 #define RC2 ((1<<3)<<8)
 155 #define RC3 ((1<<4)<<8)
 156
 157 #define DIMM0 0x50
 158 #define DIMM1 0x51
 159 #define DIMM2 0x52
 160 #define DIMM3 0x53
 161
 162 static void main(void)
 163 {
 164         static const struct mem_controller cpu[] = {
 165                 {
 166                  .node_id = 0,
 167                  .f0 = PCI_DEV(0, 0x18, 0),
 168                  .f1 = PCI_DEV(0, 0x18, 1),
 169                  .f2 = PCI_DEV(0, 0x18, 2),
 170                  .f3 = PCI_DEV(0, 0x18, 3),
 171                  .channel0 = {RC0 | DIMM0, RC0 | DIMM2, 0, 0},
 172                  .channel1 = {RC0 | DIMM1, RC0 | DIMM3, 0, 0},
 173                  },
 174                 {
 175                  .node_id = 1,
 176                  .f0 = PCI_DEV(0, 0x19, 0),
 177                  .f1 = PCI_DEV(0, 0x19, 1),
 178                  .f2 = PCI_DEV(0, 0x19, 2),
 179                  .f3 = PCI_DEV(0, 0x19, 3),
 180                  .channel0 = {RC1 | DIMM0, RC1 | DIMM2, 0, 0},
 181                  .channel1 = {RC1 | DIMM1, RC1 | DIMM3, 0, 0},
 182                  },
 183                 {
 184                  .node_id = 2,
 185                  .f0 = PCI_DEV(0, 0x1a, 0),
 186                  .f1 = PCI_DEV(0, 0x1a, 1),
 187                  .f2 = PCI_DEV(0, 0x1a, 2),
 188                  .f3 = PCI_DEV(0, 0x1a, 3),
 189                  .channel0 = {RC2 | DIMM0, RC2 | DIMM2, 0, 0},
 190                  .channel1 = {RC2 | DIMM1, RC2 | DIMM3, 0, 0},
 191                  },
 192                 {
 193                  .node_id = 3,
 194                  .f0 = PCI_DEV(0, 0x1b, 0),
 195                  .f1 = PCI_DEV(0, 0x1b, 1),
 196                  .f2 = PCI_DEV(0, 0x1b, 2),
 197                  .f3 = PCI_DEV(0, 0x1b, 3),
 198                  .channel0 = {RC3 | DIMM0, RC3 | DIMM2, 0, 0},
 199                  .channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0},
 200                  }
 201         };
 202         int needs_reset;
 203
 204         enable_lapic();
 205         init_timer();
 206
 207         if (cpu_init_detected()) {
 208                 asm("jmp __cpu_reset");
 209         }
 210
 211         distinguish_cpu_resets();
 212
 213         if (!boot_cpu()) {
 214                 stop_this_cpu();
 215         }
 216
 217         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 218         uart_init();
 219         console_init();
 220         setup_quartet_resource_map();
 221         needs_reset = setup_coherent_ht_domain();
 222         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 223         if (needs_reset) {
 224                 print_info("ht reset -\r\n");
 225                 soft_reset();
 226         }
 227 #if 0
 228         print_pci_devices();
 229 #endif
 230         enable_smbus();
 231 #if 0
 232         dump_spd_registers(&cpu[0]);
 233 #endif
 234         memreset_setup();
 235         sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
 236
 237 #if 0
 238         dump_pci_devices();
 239 #endif
 240 #if 0
 241         dump_pci_device(PCI_DEV(0, 0x18, 2));
 242 #endif
 243 #if 0
 244         /* Check the first 1M */
 245         ram_check(0x00000000, 0x000100000);
 246 #endif
 247 }