src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <device/pnp.h>
   7 #include <arch/romcc_io.h>
   8 #include "pc80/serial.c"
   9 #include "arch/i386/lib/console.c"
  10 #include "ram/ramtest.c"
  11 #include "northbridge/amd/amdk8/early_ht.c"
  12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/k8/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "cpu/p6/boot_cpu.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "debug.c"
  19
  20 static void memreset_setup(void)
  21 {
  22         /* Set the memreset low */
  23         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  24         /* Ensure the BIOS has control of the memory lines */
  25         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  26 }
  27
  28 static void memreset(int controllers, const struct mem_controller *ctrl)
  29 {
  30         udelay(800);
  31         /* Set memreset_high */
  32         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  33         udelay(90);
  34 }
  35
  36 /*
  37  * generate_row is specific to board implementation
  38  *
  39  */
  40
  41 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  42 {
  43         /* Routing Table Node i
  44          *
  45          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  46          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  47          *
  48          * [ 0: 3] Request Route
  49          *     [0] Route to this node
  50          *     [1] Route to Link 0
  51          *     [2] Route to Link 1
  52          *     [3] Route to Link 2
  53          * [11: 8] Response Route
  54          *     [0] Route to this node
  55          *     [1] Route to Link 0
  56          *     [2] Route to Link 1
  57          *     [3] Route to Link 2
  58          * [19:16] Broadcast route
  59          *     [0] Route to this node
  60          *     [1] Route to Link 0
  61          *     [2] Route to Link 1
  62          *     [3] Route to Link 2
  63          */
  64
  65         uint32_t ret=0x00010101; /* default row entry */
  66
  67         static const unsigned int rows_2p[2][2] = {
  68                 { 0x00030101, 0x00010202 },
  69                 { 0x00010202, 0x00030101 }
  70         };
  71
  72         static const unsigned int rows_4p[4][4] = {
  73                 { 0x00070101, 0x00010404, 0x00050202, 0x00010402 },
  74                 { 0x00010808, 0x000b0101, 0x00010802, 0x00090202 },
  75                 { 0x00090202, 0x00010802, 0x000b0101, 0x00010808 },
  76                 { 0x00010402, 0x00050202, 0x00010404, 0x00070101 }
  77         };
  78
  79         if (!(node>=maxnodes || row>=maxnodes)) {
  80                 if (maxnodes==2)
  81                         ret=rows_2p[node][row];
  82                 if (maxnodes==4)
  83                         ret=rows_4p[node][row];
  84         }
  85
  86         return ret;
  87 }
  88
  89 static inline int spd_read_byte(unsigned device, unsigned address)
  90 {
  91         return smbus_read_byte(device, address);
  92 }
  93
  94 #include "northbridge/amd/amdk8/cpu_ldtstop.c"
  95 #include "southbridge/amd/amd8111/amd8111_ldtstop.c"
  96
  97 #include "northbridge/amd/amdk8/raminit.c"
  98 #include "northbridge/amd/amdk8/coherent_ht.c"
  99 #include "sdram/generic_sdram.c"
 100
 101 #include "resourcemap.c" /* quartet does not want the default */
 102
 103 static void enable_lapic(void)
 104 {
 105
 106         msr_t msr;
 107         msr = rdmsr(0x1b);
 108         msr.hi &= 0xffffff00;
 109         msr.lo &= 0x000007ff;
 110         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
 111         wrmsr(0x1b, msr);
 112 }
 113
 114 static void stop_this_cpu(void)
 115 {
 116         unsigned apicid;
 117         apicid = apic_read(APIC_ID) >> 24;
 118
 119         /* Send an APIC INIT to myself */
 120         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 121         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 122         /* Wait for the ipi send to finish */
 123         apic_wait_icr_idle();
 124
 125         /* Deassert the APIC INIT */
 126         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 127         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 128         /* Wait for the ipi send to finish */
 129         apic_wait_icr_idle();
 130
 131         /* If I haven't halted spin forever */
 132         for(;;) {
 133                 hlt();
 134         }
 135 }
 136
 137 #define PC87360_FDC  0x00
 138 #define PC87360_PP   0x01
 139 #define PC87360_SP2  0x02
 140 #define PC87360_SP1  0x03
 141 #define PC87360_SWC  0x04
 142 #define PC87360_KBCM 0x05
 143 #define PC87360_KBCK 0x06
 144 #define PC87360_GPIO 0x07
 145 #define PC87360_ACB  0x08
 146 #define PC87360_FSCM 0x09
 147 #define PC87360_WDT  0x0A
 148
 149 static void pc87360_enable_serial(void)
 150 {
 151         pnp_set_logical_device(SIO_BASE, PC87360_SP1);
 152         pnp_set_enable(SIO_BASE, 1);
 153         pnp_set_iobase0(SIO_BASE, 0x3f8);
 154 }
 155
 156 static void main(void)
 157 {
 158         /*
 159          * GPIO28 of 8111 will control H0_MEMRESET_L
 160          * GPIO29 of 8111 will control H1_MEMRESET_L
 161          */
 162
 163         static const struct mem_controller cpu[] = {
 164                 {
 165                         .node_id = 0,
 166                         .f0 = PCI_DEV(0, 0x18, 0),
 167                         .f1 = PCI_DEV(0, 0x18, 1),
 168                         .f2 = PCI_DEV(0, 0x18, 2),
 169                         .f3 = PCI_DEV(0, 0x18, 3),
 170                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 171                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 172                 },
 173                 {
 174                         .node_id = 1,
 175                         .f0 = PCI_DEV(0, 0x19, 0),
 176                         .f1 = PCI_DEV(0, 0x19, 1),
 177                         .f2 = PCI_DEV(0, 0x19, 2),
 178                         .f3 = PCI_DEV(0, 0x19, 3),
 179                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 180                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 181                 },
 182                 {
 183                         .node_id = 2,
 184                         .f0 = PCI_DEV(0, 0x1a, 0),
 185                         .f1 = PCI_DEV(0, 0x1a, 1),
 186                         .f2 = PCI_DEV(0, 0x1a, 2),
 187                         .f3 = PCI_DEV(0, 0x1a, 3),
 188                         .channel0 = { (0xa<<3)|8, (0xa<<3)|10, 0, 0 },
 189                         .channel1 = { (0xa<<3)|9, (0xa<<3)|11, 0, 0 },
 190                 },
 191                 {
 192                         .node_id = 3,
 193                         .f0 = PCI_DEV(0, 0x1b, 0),
 194                         .f1 = PCI_DEV(0, 0x1b, 1),
 195                         .f2 = PCI_DEV(0, 0x1b, 2),
 196                         .f3 = PCI_DEV(0, 0x1b, 3),
 197                         .channel0 = { (0xa<<3)|12, (0xa<<3)|14, 0, 0 },
 198                         .channel1 = { (0xa<<3)|13, (0xa<<3)|15, 0, 0 },
 199                 }
 200         };
 201         if (cpu_init_detected()) {
 202                 asm("jmp __cpu_reset");
 203         }
 204         enable_lapic();
 205         init_timer();
 206         if (!boot_cpu()) {
 207                 notify_bsp_ap_is_stopped();
 208                 stop_this_cpu();
 209         }
 210         pc87360_enable_serial();
 211         uart_init();
 212         console_init();
 213         setup_quartet_resource_map();
 214         setup_coherent_ht_domain();
 215         enumerate_ht_chain(0);
 216         distinguish_cpu_resets(0);
 217
 218 #if 0
 219         print_pci_devices();
 220 #endif
 221         enable_smbus();
 222 #if 0
 223         dump_spd_registers(&cpu[0]);
 224 #endif
 225         memreset_setup();
 226         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 227
 228 #if 0
 229         dump_pci_devices();
 230 #endif
 231 #if 0
 232         dump_pci_device(PCI_DEV(0, 0x18, 2));
 233 #endif
 234
 235         /* Check all of memory */
 236 #if 0
 237         msr_t msr;
 238         msr = rdmsr(TOP_MEM);
 239         print_debug("TOP_MEM: ");
 240         print_debug_hex32(msr.hi);
 241         print_debug_hex32(msr.lo);
 242         print_debug("\r\n");
 243 #endif
 244 #if 0
 245         ram_check(0x00000000, msr.lo);
 246 #else
 247         /* Check 16MB of memory */
 248         ram_check(0x00000000, 0x01000000);
 249 #endif
 250 }