src/mainboard/amd/quartet/auto.c

   1 #define ASSEMBLY 1
   2 //#define MAXIMUM_CONSOLE_LOGLEVEL 9
   3 //#define DEFAULT_CONSOLE_LOGLEVEL 9
   4
   5 #include <stdint.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <arch/cpu.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "ram/ramtest.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include <cpu/amd/model_fxx_rev.h>
  25 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  26 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  30
  31 static void hard_reset(void)
  32 {
  33         set_bios_reset();
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 /*
  47  * GPIO28 of 8111 will control H0_MEMRESET_L
  48  * GPIO29 of 8111 will control H1_MEMRESET_L
  49  */
  50 static void memreset_setup(void)
  51 {
  52         if (is_cpu_pre_c0()) {
  53                 /* Set the memreset low */
  54                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  55                      (0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
  56                 /* Ensure the BIOS has control of the memory lines */
  57                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  58                      (0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
  59         } else {
  60                 /* Ensure the CPU has controll of the memory lines */
  61                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  62                      (1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
  63         }
  64 }
  65
  66 static void memreset(int controllers, const struct mem_controller *ctrl)
  67 {
  68         if (is_cpu_pre_c0()) {
  69                 udelay(800);
  70                 /* Set memreset_high */
  71                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  72                      (1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
  73                 udelay(90);
  74         }
  75 }
  76
  77 /*
  78  * generate_row is specific to board implementation
  79  *
  80  */
  81
  82 static unsigned int generate_row(uint8_t node, uint8_t row,
  83                                  uint8_t maxnodes)
  84 {
  85         /* Routing Table Node i
  86          *
  87          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  88          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  89          *
  90          * [ 0: 3] Request Route
  91          *     [0] Route to this node
  92          *     [1] Route to Link 0
  93          *     [2] Route to Link 1
  94          *     [3] Route to Link 2
  95          * [11: 8] Response Route
  96          *     [0] Route to this node
  97          *     [1] Route to Link 0
  98          *     [2] Route to Link 1
  99          *     [3] Route to Link 2
 100          * [19:16] Broadcast route
 101          *     [0] Route to this node
 102          *     [1] Route to Link 0
 103          *     [2] Route to Link 1
 104          *     [3] Route to Link 2
 105          */
 106
 107         uint32_t ret = 0x00010101;      /* default row entry */
 108 /*
 109         static const unsigned int rows_2p[2][2] = {
 110                 {0x00030101, 0x00010202},
 111                 {0x00010202, 0x00030101}
 112         };
 113 */
 114
 115         static const unsigned int rows_4p[4][4] = {
 116                 {0x00070101, 0x00010202, 0x00030404, 0x00010204},
 117                 {0x00010202, 0x000b0101, 0x00010208, 0x00030808},
 118                 {0x00030808, 0x00010208, 0x000b0101, 0x00010202},
 119                 {0x00010204, 0x00030404, 0x00010202, 0x00070101}
 120         };
 121
 122         if (!(node >= maxnodes || row >= maxnodes)) {
 123 /*
 124                 if (maxnodes == 2)
 125                         ret = rows_2p[node][row];
 126                 if (maxnodes == 4)
 127 */
 128                         ret = rows_4p[node][row];
 129         }
 130
 131         return ret;
 132 }
 133
 134
 135 #if ( FAKE_SPDROM != 1 )
 136 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 137 {
 138 #define SMBUS_HUB 0x18
 139         unsigned device = (ctrl->channel0[0]) >> 8;
 140         smbus_write_byte(SMBUS_HUB, 0x01, device);
 141         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 142 }
 143
 144 static inline int spd_read_byte(unsigned device, unsigned address)
 145 {
 146         return smbus_read_byte(device & 0xff, address);
 147 }
 148 #else
 149 #include "fakespd.c"
 150 #endif
 151
 152 // #include "northbridge/amd/amdk8/setup_resource_map.c"
 153 #include "northbridge/amd/amdk8/raminit.c"
 154 #include "northbridge/amd/amdk8/coherent_ht.c"
 155 #include "northbridge/amd/amdk8/incoherent_ht.c"
 156 #include "cpu/amd/dualcore/dualcore.c"
 157
 158 #include "sdram/generic_sdram.c"
 159 /* quartet does not want the default */
 160 #include "resourcemap.c"
 161
 162 #define RC0 ((1<<1)<<8)
 163 #define RC1 ((1<<2)<<8)
 164 #define RC2 ((1<<3)<<8)
 165 #define RC3 ((1<<4)<<8)
 166
 167 #define DIMM0 0x50
 168 #define DIMM1 0x51
 169 #define DIMM2 0x52
 170 #define DIMM3 0x53
 171
 172 static void main(unsigned long bist)
 173 {
 174         static const struct mem_controller cpu[] = {
 175                 {
 176                  .node_id = 0,
 177                  .f0 = PCI_DEV(0, 0x18, 0),
 178                  .f1 = PCI_DEV(0, 0x18, 1),
 179                  .f2 = PCI_DEV(0, 0x18, 2),
 180                  .f3 = PCI_DEV(0, 0x18, 3),
 181                  .channel0 = {RC0 | DIMM0, RC0 | DIMM2, 0, 0},
 182                  .channel1 = {RC0 | DIMM1, RC0 | DIMM3, 0, 0},
 183                  },
 184                 {
 185                  .node_id = 1,
 186                  .f0 = PCI_DEV(0, 0x19, 0),
 187                  .f1 = PCI_DEV(0, 0x19, 1),
 188                  .f2 = PCI_DEV(0, 0x19, 2),
 189                  .f3 = PCI_DEV(0, 0x19, 3),
 190                  .channel0 = {RC1 | DIMM0, RC1 | DIMM2, 0, 0},
 191                  .channel1 = {RC1 | DIMM1, RC1 | DIMM3, 0, 0},
 192                  },
 193                 {
 194                  .node_id = 2,
 195                  .f0 = PCI_DEV(0, 0x1a, 0),
 196                  .f1 = PCI_DEV(0, 0x1a, 1),
 197                  .f2 = PCI_DEV(0, 0x1a, 2),
 198                  .f3 = PCI_DEV(0, 0x1a, 3),
 199                  .channel0 = {RC2 | DIMM0, RC2 | DIMM2, 0, 0},
 200                  .channel1 = {RC2 | DIMM1, RC2 | DIMM3, 0, 0},
 201                  },
 202                 {
 203                  .node_id = 3,
 204                  .f0 = PCI_DEV(0, 0x1b, 0),
 205                  .f1 = PCI_DEV(0, 0x1b, 1),
 206                  .f2 = PCI_DEV(0, 0x1b, 2),
 207                  .f3 = PCI_DEV(0, 0x1b, 3),
 208                  .channel0 = {RC3 | DIMM0, RC3 | DIMM2, 0, 0},
 209                  .channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0},
 210                  }
 211         };
 212
 213         int needs_reset;
 214         unsigned nodeid;
 215
 216         if (bist == 0) {
 217                 k8_init_and_stop_secondaries();
 218         }
 219         /* Setup the console */
 220         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 221         uart_init();
 222         console_init();
 223
 224         /* Halt if there was a built in self test failure */
 225         report_bist_failure(bist);
 226
 227         setup_quartet_resource_map();
 228         needs_reset = setup_coherent_ht_domain();
 229 #if 0
 230         needs_reset |= ht_setup_chains(2);
 231 #else
 232         needs_reset |= ht_setup_chains_x();
 233 #endif
 234         if (needs_reset) {
 235                 print_info("ht reset -\r\n");
 236                 soft_reset();
 237         }
 238 #if 0
 239         print_pci_devices();
 240 #endif
 241         enable_smbus();
 242 #if 0
 243         dump_spd_registers(&cpu[0]);
 244 #endif
 245         memreset_setup();
 246         sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
 247
 248 #if 0
 249         dump_pci_devices();
 250 #endif
 251 #if 0
 252         dump_pci_device(PCI_DEV(0, 0x18, 2));
 253 #endif
 254 #if 0
 255         /* Check the first 1M */
 256         ram_check(0x00000000, 0x000100000);
 257 #endif
 258 }