3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
28 uses LB_CKS_RANGE_START
31 uses MAINBOARD_PART_NUMBER
34 uses LINUXBIOS_EXTRA_VERSION
39 uses DEFAULT_CONSOLE_LOGLEVEL
40 uses MAXIMUM_CONSOLE_LOGLEVEL
41 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
42 uses CONFIG_CONSOLE_SERIAL8250
56 ## ROM_SIZE is the size of boot ROM that this board will use.
58 default ROM_SIZE=524288
61 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
63 default FALLBACK_SIZE=0x40000
66 ## Build code for the fallback boot
68 default HAVE_FALLBACK_BOOT=1
71 ## Build code to reset the motherboard from linuxBIOS
73 default HAVE_HARD_RESET=1
76 ## Build code to export a programmable irq routing table
78 default HAVE_PIRQ_TABLE=1
79 default IRQ_SLOT_COUNT=9
82 ## Build code to export an x86 MP table
83 ## Useful for specifying IRQ routing values
85 default HAVE_MP_TABLE=1
88 ## Build code to export a CMOS option table
90 default HAVE_OPTION_TABLE=1
93 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
95 default LB_CKS_RANGE_START=49
96 default LB_CKS_RANGE_END=122
97 default LB_CKS_LOC=123
100 ## Build code for SMP support
101 ## Only worry about 2 micro processors
104 default CONFIG_MAX_CPUS=4
105 default CONFIG_MAX_PHYSICAL_CPUS=4
108 ## Build code to setup a generic IOAPIC
110 default CONFIG_IOAPIC=1
113 ## Clean up the motherboard id strings
115 default MAINBOARD_PART_NUMBER="QUARTET"
116 default MAINBOARD_VENDOR="AMD"
119 ### LinuxBIOS layout values
122 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
123 default ROM_IMAGE_SIZE = 65536
126 ## Use a small 8K stack
128 default STACK_SIZE=0x2000
131 ## Use a small 16K heap
133 default HEAP_SIZE=0x4000
136 ## Only use the option table in a normal image
138 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
141 ## LinuxBIOS C code runs at this location in RAM
143 default _RAMBASE=0x00004000
146 ## Load the payload from the ROM
148 default CONFIG_ROM_PAYLOAD = 1
151 ### Defaults of options that you may want to override in the target config file
155 ## The default compiler
157 default CC="$(CROSS_COMPILE)gcc -m32"
161 ## The Serial Console
164 # To Enable the Serial Console
165 default CONFIG_CONSOLE_SERIAL8250=1
167 ## Select the serial console baud rate
168 default TTYS0_BAUD=115200
169 #default TTYS0_BAUD=57600
170 #default TTYS0_BAUD=38400
171 #default TTYS0_BAUD=19200
172 #default TTYS0_BAUD=9600
173 #default TTYS0_BAUD=4800
174 #default TTYS0_BAUD=2400
175 #default TTYS0_BAUD=1200
177 # Select the serial console base port
178 default TTYS0_BASE=0x3f8
180 # Select the serial protocol
181 # This defaults to 8 data bits, 1 stop bit, and no parity
182 default TTYS0_LCS=0x3
185 ### Select the linuxBIOS loglevel
187 ## EMERG 1 system is unusable
188 ## ALERT 2 action must be taken immediately
189 ## CRIT 3 critical conditions
190 ## ERR 4 error conditions
191 ## WARNING 5 warning conditions
192 ## NOTICE 6 normal but significant condition
193 ## INFO 7 informational
194 ## DEBUG 8 debug-level messages
195 ## SPEW 9 Way too many details
197 ## Request this level of debugging output
198 default DEFAULT_CONSOLE_LOGLEVEL=8
199 ## At a maximum only compile in this level of debugging
200 default MAXIMUM_CONSOLE_LOGLEVEL=8
203 ## Select power on after power fail setting
204 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"