src/mainboard/amd/pistachio/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define RAMINIT_SYSINFO 1
  21 #define SET_FIDVID 1
  22 #define QRANK_DIMM_SUPPORT 1
  23 #if CONFIG_LOGICAL_CPUS==1
  24 #define SET_NB_CFG_54 1
  25 #endif
  26
  27 #define DIMM0 0x50
  28 #define DIMM1 0x51
  29
  30 #include <stdint.h>
  31 #include <string.h>
  32 #include <device/pci_def.h>
  33 #include <arch/io.h>
  34 #include <device/pnp_def.h>
  35 #include <arch/romcc_io.h>
  36 #include <cpu/x86/lapic.h>
  37 #include "option_table.h"
  38 #include "pc80/mc146818rtc_early.c"
  39 #include "pc80/serial.c"
  40 #include "console/console.c"
  41
  42 #include <cpu/amd/model_fxx_rev.h>
  43 #include "northbridge/amd/amdk8/raminit.h"
  44 #include "cpu/amd/model_fxx/apic_timer.c"
  45 #include "lib/delay.c"
  46
  47 #include "cpu/x86/lapic/boot_cpu.c"
  48 #include "northbridge/amd/amdk8/reset_test.c"
  49 #include "superio/ite/it8712f/it8712f_early_serial.c"
  50
  51 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  52 #include "cpu/x86/bist.h"
  53
  54 #include "northbridge/amd/amdk8/setup_resource_map.c"
  55
  56 #include "southbridge/amd/rs690/rs690_early_setup.c"
  57 #include "southbridge/amd/sb600/sb600_early_setup.c"
  58 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
  59
  60 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 /* called in raminit_f.c */
  66 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  67 {
  68 }
  69
  70 /*called in raminit_f.c */
  71 static inline int spd_read_byte(u32 device, u32 address)
  72 {
  73         return smbus_read_byte(device, address);
  74 }
  75
  76 #include "northbridge/amd/amdk8/amdk8.h"
  77 #include "northbridge/amd/amdk8/incoherent_ht.c"
  78 #include "northbridge/amd/amdk8/raminit_f.c"
  79 #include "northbridge/amd/amdk8/coherent_ht.c"
  80 #include "lib/generic_sdram.c"
  81 #include "resourcemap.c"
  82
  83 #include "cpu/amd/dualcore/dualcore.c"
  84
  85
  86 #include "cpu/amd/car/post_cache_as_ram.c"
  87
  88 #include "cpu/amd/model_fxx/init_cpus.c"
  89
  90 #include "cpu/amd/model_fxx/fidvid.c"
  91
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  97         int needs_reset = 0;
  98         u32 bsp_apicid = 0;
  99         msr_t msr;
 100         struct cpuid_result cpuid1;
 101         struct sys_info *sysinfo =
 102             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
 103                                 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 104
 105         if (!cpu_init_detectedx && boot_cpu()) {
 106                 /* Nothing special needs to be done to find bus 0 */
 107                 /* Allow the HT devices to be found */
 108                 enumerate_ht_chain();
 109
 110                 sb600_lpc_port80();
 111                 /* sb600_pci_port80(); */
 112         }
 113
 114         if (bist == 0) {
 115                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 116         }
 117
 118         enable_rs690_dev8();
 119         sb600_lpc_init();
 120
 121         /* Pistachio used a FPGA to enable serial debug instead of a SIO
 122          * and it doens't require any special setup. */
 123         uart_init();
 124         console_init();
 125
 126         post_code(0x03);
 127
 128         /* Halt if there was a built in self test failure */
 129         report_bist_failure(bist);
 130         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 131
 132         setup_pistachio_resource_map();
 133
 134         setup_coherent_ht_domain();
 135
 136 #if CONFIG_LOGICAL_CPUS==1
 137         /* It is said that we should start core1 after all core0 launched */
 138         wait_all_core0_started();
 139         start_other_cores();
 140 #endif
 141         wait_all_aps_started(bsp_apicid);
 142
 143         /* it will set up chains and store link pair for optimization later,
 144          * it will init sblnk and sbbusn, nodes, sbdn */
 145         ht_setup_chains_x(sysinfo);
 146
 147         /* run _early_setup before soft-reset. */
 148         rs690_early_setup();
 149         sb600_early_setup();
 150
 151         post_code(0x04);
 152
 153         /* Check to see if processor is capable of changing FIDVID  */
 154         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 155         cpuid1 = cpuid(0x80000007);
 156         if( (cpuid1.edx & 0x6) == 0x6 ) {
 157
 158                 /* Read FIDVID_STATUS */
 159                 msr=rdmsr(0xc0010042);
 160                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 161
 162                 enable_fid_change();
 163                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 164                 init_fidvid_bsp(bsp_apicid);
 165
 166                 /* show final fid and vid */
 167                 msr=rdmsr(0xc0010042);
 168                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 169
 170         } else {
 171                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 172         }
 173
 174         post_code(0x05);
 175
 176         needs_reset = optimize_link_coherent_ht();
 177         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 178         rs690_htinit();
 179         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 180
 181         post_code(0x06);
 182
 183         if (needs_reset) {
 184                 print_info("ht reset -\n");
 185                 soft_reset();
 186         }
 187
 188         allow_all_aps_stop(bsp_apicid);
 189
 190         /* It's the time to set ctrl now; */
 191         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 192                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 193         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 194
 195         post_code(0x07);
 196
 197         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 198
 199         post_code(0x08);
 200
 201         rs690_before_pci_init();
 202         sb600_before_pci_init();
 203
 204         post_cache_as_ram();
 205 }
 206