src/mainboard/amd/pistachio/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <stdint.h>
  21 #include <string.h>
  22 #include <device/pci_def.h>
  23 #include <arch/io.h>
  24 #include <device/pnp_def.h>
  25 #include <arch/romcc_io.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <pc80/mc146818rtc.h>
  28 #include <console/console.h>
  29 #include <cpu/amd/model_fxx_rev.h>
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "superio/ite/it8712f/early_serial.c"
  36 #include <spd.h>
  37 #include "cpu/x86/mtrr/earlymtrr.c"
  38 #include "cpu/x86/bist.h"
  39 #include "northbridge/amd/amdk8/setup_resource_map.c"
  40 #include "southbridge/amd/rs690/early_setup.c"
  41 #include "southbridge/amd/sb600/early_setup.c"
  42 #include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */
  43
  44 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  45 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  46
  47 static inline int spd_read_byte(u32 device, u32 address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 #include "northbridge/amd/amdk8/amdk8.h"
  53 #include "northbridge/amd/amdk8/incoherent_ht.c"
  54 #include "northbridge/amd/amdk8/raminit_f.c"
  55 #include "northbridge/amd/amdk8/coherent_ht.c"
  56 #include "lib/generic_sdram.c"
  57 #include "resourcemap.c"
  58 #include "cpu/amd/dualcore/dualcore.c"
  59 #include "cpu/amd/car/post_cache_as_ram.c"
  60 #include "cpu/amd/model_fxx/init_cpus.c"
  61 #include "cpu/amd/model_fxx/fidvid.c"
  62 #include "northbridge/amd/amdk8/early_ht.c"
  63
  64 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  65 {
  66         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  67         int needs_reset = 0;
  68         u32 bsp_apicid = 0;
  69         msr_t msr;
  70         struct cpuid_result cpuid1;
  71         struct sys_info *sysinfo =
  72             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
  73                                 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  74
  75         if (!cpu_init_detectedx && boot_cpu()) {
  76                 /* Nothing special needs to be done to find bus 0 */
  77                 /* Allow the HT devices to be found */
  78                 enumerate_ht_chain();
  79                 sb600_lpc_port80();
  80                 /* sb600_pci_port80(); */
  81         }
  82
  83         if (bist == 0)
  84                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  85
  86         enable_rs690_dev8();
  87         sb600_lpc_init();
  88
  89         /* Pistachio used a FPGA to enable serial debug instead of a SIO
  90          * and it doesn't require any special setup. */
  91
  92         console_init();
  93
  94         post_code(0x03);
  95
  96         /* Halt if there was a built in self test failure */
  97         report_bist_failure(bist);
  98         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
  99
 100         setup_pistachio_resource_map();
 101
 102         setup_coherent_ht_domain();
 103
 104 #if CONFIG_LOGICAL_CPUS==1
 105         /* It is said that we should start core1 after all core0 launched */
 106         wait_all_core0_started();
 107         start_other_cores();
 108 #endif
 109         wait_all_aps_started(bsp_apicid);
 110
 111         /* it will set up chains and store link pair for optimization later,
 112          * it will init sblnk and sbbusn, nodes, sbdn */
 113         ht_setup_chains_x(sysinfo);
 114
 115         /* run _early_setup before soft-reset. */
 116         rs690_early_setup();
 117         sb600_early_setup();
 118
 119         post_code(0x04);
 120
 121         /* Check to see if processor is capable of changing FIDVID  */
 122         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 123         cpuid1 = cpuid(0x80000007);
 124         if ((cpuid1.edx & 0x6) == 0x6) {
 125                 /* Read FIDVID_STATUS */
 126                 msr=rdmsr(0xc0010042);
 127                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 128
 129                 enable_fid_change();
 130                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 131                 init_fidvid_bsp(bsp_apicid);
 132
 133                 /* show final fid and vid */
 134                 msr=rdmsr(0xc0010042);
 135                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 136         } else {
 137                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 138         }
 139
 140         post_code(0x05);
 141
 142         needs_reset = optimize_link_coherent_ht();
 143         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 144         rs690_htinit();
 145         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 146
 147         post_code(0x06);
 148
 149         if (needs_reset) {
 150                 print_info("ht reset -\n");
 151                 soft_reset();
 152         }
 153
 154         allow_all_aps_stop(bsp_apicid);
 155
 156         /* It's the time to set ctrl now; */
 157         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 158                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 159         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 160
 161         post_code(0x07);
 162
 163         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 164
 165         post_code(0x08);
 166
 167         rs690_before_pci_init();
 168         sb600_before_pci_init();
 169
 170         post_cache_as_ram();
 171 }