2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/coreboot_tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
30 #define ADT7475_ADDRESS 0x2E
31 #define SMBUS_IO_BASE 0x1000
33 extern u8 pm_ioread(u8 reg);
34 extern void pm_iowrite(u8 reg, u8 value);
35 extern u8 pm2_ioread(u8 reg);
36 extern void pm2_iowrite(u8 reg, u8 value);
37 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
38 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
40 #define ADT7475_read_byte(address) \
41 do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
42 #define ADT7475_write_byte(address, val) \
43 do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
45 unsigned long uma_memory_start, uma_memory_size;
47 /********************************************************
48 * pistachio uses a BCM5787 as on-board NIC.
49 * It has a pin named LOW_POWER to enable it into LOW POWER state.
50 * In order to run NIC, we should let it out of Low power state. This pin is
52 * RPR4.2.3 GPM as GPIO
53 * GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
54 * I/O C50, C51, C52, PM I/O94, 95, 96.
55 * RPR4.2.3.1 GPM pins as Input
56 * RPR4.2.3.2 GPM pins as Output
57 * The R77 (on BRASS) / R81 (on Bronze) is not load!
58 * So NIC can work whether this function runs.
59 ********************************************************/
60 static void enable_onboard_nic()
64 printk_info("enable_onboard_nic.\n");
66 /* enable GPM8 output */
67 byte = pm_ioread(0x95);
69 pm_iowrite(0x95, byte);
71 /* GPM8 outputs low. */
72 byte = pm_ioread(0x94);
74 pm_iowrite(0x94, byte);
80 static void set_thermal_config()
89 ADT7475_write_byte(0x40, 0x04);
90 /* Config Register 6 */
91 ADT7475_write_byte(0x10, 0x00);
92 /* Config Register 7 */
93 ADT7475_write_byte(0x11, 0x00);
95 /* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
96 ADT7475_write_byte(0x7c, 0xa0);
97 /* No offset for remote 2 */
98 ADT7475_write_byte(0x72, 0x00);
99 /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
100 ADT7475_write_byte(0x5c, 0x02);
101 /* PWM 3 configuration register Case fan controlled by 690 temp */
102 ADT7475_write_byte(0x5e, 0x42);
104 /* remote 1 low temp limit */
105 ADT7475_write_byte(0x4e, 0x00);
106 /* remote 1 High temp limit (90C) */
107 ADT7475_write_byte(0x4f, 0x9a);
109 /* remote2 Low Temp Limit */
110 ADT7475_write_byte(0x52, 0x00);
111 /* remote2 High Limit (90C) */
112 ADT7475_write_byte(0x53, 0x9a);
114 /* remote 1 therm temp limit (95C) */
115 ADT7475_write_byte(0x6a, 0x9f);
116 /* remote 2 therm temp limit (95C) */
117 ADT7475_write_byte(0x6c, 0x9f);
119 /* PWM 1 minimum duty cycle (37%) */
120 ADT7475_write_byte(0x64, 0x60);
121 /* PWM 1 Maximum duty cycle (100%) */
122 ADT7475_write_byte(0x38, 0xff);
123 /* PWM 3 minimum duty cycle (37%) */
124 ADT7475_write_byte(0x66, 0x60);
125 /* PWM 3 Maximum Duty Cycle (100%) */
126 ADT7475_write_byte(0x3a, 0xff);
128 /* Remote 1 temperature Tmin (32C) */
129 ADT7475_write_byte(0x67, 0x60);
130 /* Remote 2 temperature Tmin (32C) */
131 ADT7475_write_byte(0x69, 0x60);
132 /* remote 1 Trange (53C ramp range) */
133 ADT7475_write_byte(0x5f, 0xe8);
134 /* remote 2 Trange (53C ramp range) */
135 ADT7475_write_byte(0x61, 0xe8);
137 /* PWM2 Duty cycle */
138 ADT7475_write_byte(0x65, 0x00);
140 ADT7475_write_byte(0x5d, 0x80);
141 /* PWM2 Max Duty Cycle */
142 ADT7475_write_byte(0x39, 0x00);
144 /* Config Register 3 - enable smbalert & therm */
145 ADT7475_write_byte(0x78, 0x03);
146 /* Config Register 4 - enable therm output */
147 ADT7475_write_byte(0x7d, 0x09);
148 /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
149 ADT7475_write_byte(0x75, 0x2a);
150 /* Config Register 1 Set Start bit */
151 ADT7475_write_byte(0x40, 0x05);
152 /* Read status register to clear any old errors */
153 byte2 = ADT7475_read_byte(0x42);
154 byte = ADT7475_read_byte(0x41);
156 /* remote 1 temperature offset */
157 ADT7475_write_byte(0x70, 0x00);
159 printk_info("Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
162 /* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
163 /* set GPM5 as GPM5, not DDR3_memory disable */
164 byte = pm_ioread(0x8f);
165 byte |= 1 << 6; /* enable GPE */
166 pm_iowrite(0x8f, byte);
168 /* GPM5 as GPIO not USB OC */
169 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
171 pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
172 sm_dev->path.u.pci.devfn, 0x64);
174 pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
175 sm_dev->path.u.pci.devfn, 0x64, dword);
177 /* Enable Client Management Index/Data registers */
179 pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
180 sm_dev->path.u.pci.devfn, 0x78);
181 dword |= 1 << 11; /* Cms_enable */
182 pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
183 sm_dev->path.u.pci.devfn, 0x78, dword);
187 pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
188 sm_dev->path.u.pci.devfn, 0x41);
190 pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
191 sm_dev->path.u.pci.devfn, 0x41, byte);
193 /* set GPM5 as input */
194 /* step1: set index register 0C50h to 13h (miscellaneous control) */
195 outb(0x13, 0xC50); /* CMIndex */
196 /* step2: set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
197 byte = inb(0xC51); /* CMData */
201 /* step3: set GPM port 0C52h appropriate bits to 1 to tri-state the GPM port */
202 byte = inb(0xc52); /* GpmPort */
205 /* step4: set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
210 /* trigger SCI/SMI */
211 byte = pm_ioread(0x34);
213 pm_iowrite(0x34, byte);
215 /* set GPM5 to not wake from s5 */
216 byte = pm_ioread(0x77);
218 pm_iowrite(0x77, byte);
220 /* trigger on falling edge */
221 byte = pm_ioread(0x38);
223 pm_iowrite(0x38, byte);
225 /* set SB600 GPIO 64 to GPIO with pull-up */
226 byte = pm2_ioread(0x42);
228 pm2_iowrite(0x42, byte);
230 /* set GPIO 64 to input */
232 pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
233 sm_dev->path.u.pci.devfn, 0x56);
235 pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
236 sm_dev->path.u.pci.devfn, 0x56, word);
238 /* set GPIO 64 internal pull-up */
239 byte = pm2_ioread(0xf0);
241 pm2_iowrite(0xf0, byte);
243 /* set Talert to be active low */
244 byte = pm_ioread(0x67);
246 pm_iowrite(0x67, byte);
248 /* set Talert to generate ACPI event */
249 byte = pm_ioread(0x3c);
251 pm_iowrite(0x3c, byte);
254 /* byte = pm_ioread(0x68);
256 * pm_iowrite(0x68, byte);
258 * byte = pm_ioread(0x55);
260 * pm_iowrite(0x55, byte);
262 * byte = pm_ioread(0x67);
263 * byte &= ~( 1 << 6);
264 * pm_iowrite(0x67, byte);
268 /*************************************************
269 * enable the dedicated function in pistachio board.
270 * This function called early than rs690_enable.
271 *************************************************/
272 void pistachio_enable(device_t dev)
274 struct mainboard_amd_pistachio_config *mainboard =
275 (struct mainboard_amd_pistachio_config *)dev->chip_info;
277 printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev);
279 #if (CONFIG_GFXUMA == 1)
282 /* TOP_MEM: the top of DRAM below 4G */
283 msr = rdmsr(TOP_MEM);
285 ("pistachio_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
288 /* TOP_MEM2: the top of DRAM above 4G */
289 msr2 = rdmsr(TOP_MEM2);
291 ("pistachio_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
295 case 0x10000000: /* 256M system memory */
296 uma_memory_size = 0x2000000; /* 32M recommended UMA */
299 case 0x18000000: /* 384M system memory */
300 uma_memory_size = 0x4000000; /* 64M recommended UMA */
303 case 0x20000000: /* 512M system memory */
304 uma_memory_size = 0x4000000; /* 64M recommended UMA */
307 default: /* 1GB and above system memory */
308 uma_memory_size = 0x8000000; /* 128M recommended UMA */
312 uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
313 printk_info("pistachio_enable: uma size 0x%08x, memory start 0x%08x\n",
314 uma_memory_size, uma_memory_start);
318 uma_memory_size = 0x8000000; /* 128M recommended UMA */
319 uma_memory_start = 0x38000000; /* 1GB system memory supposed */
322 enable_onboard_nic();
324 set_thermal_config();
327 int add_mainboard_resources(struct lb_memory *mem)
329 /* UMA is removed from system memory in the northbridge code, but
330 * in some circumstances we want the memory mentioned as reserved.
332 #if (CONFIG_GFXUMA == 1)
333 printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
334 uma_memory_start, uma_memory_size);
335 lb_add_memory_range(mem, LB_MEM_RESERVED,
336 uma_memory_start, uma_memory_size);
341 * CONFIG_CHIP_NAME defined in Option.lb.
343 struct chip_operations mainboard_amd_pistachio_ops = {
344 CHIP_NAME("AMD Pistachio Mainboard")
345 .enable_dev = pistachio_enable,