src/mainboard/amd/pistachio/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define ASSEMBLY 1
  21 #define __ROMCC__
  22
  23 #define RAMINIT_SYSINFO 1
  24 #define K8_SET_FIDVID 1
  25 #define QRANK_DIMM_SUPPORT 1
  26 #if CONFIG_LOGICAL_CPUS==1
  27 #define SET_NB_CFG_54 1
  28 #endif
  29
  30 #define DIMM0 0x50
  31 #define DIMM1 0x51
  32
  33 #include <stdint.h>
  34 #include <device/pci_def.h>
  35 #include <arch/io.h>
  36 #include <device/pnp_def.h>
  37 #include <arch/romcc_io.h>
  38 #include <cpu/x86/lapic.h>
  39 #include "option_table.h"
  40 #include "pc80/mc146818rtc_early.c"
  41 #include "pc80/serial.c"
  42 #include "arch/i386/lib/console.c"
  43
  44 #define post_code(x) outb(x, 0x80)
  45
  46 #include <cpu/amd/model_fxx_rev.h>
  47 #include "northbridge/amd/amdk8/raminit.h"
  48 #include "cpu/amd/model_fxx/apic_timer.c"
  49 #include "lib/delay.c"
  50
  51 #if CONFIG_USE_INIT == 0
  52 #include "lib/memcpy.c"
  53 #endif
  54
  55 #include "cpu/x86/lapic/boot_cpu.c"
  56 #include "northbridge/amd/amdk8/reset_test.c"
  57 #include "northbridge/amd/amdk8/debug.c"
  58 #include "superio/ite/it8712f/it8712f_early_serial.c"
  59
  60 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  61 #include "cpu/x86/bist.h"
  62
  63 #include "northbridge/amd/amdk8/setup_resource_map.c"
  64
  65 #include "southbridge/amd/rs690/rs690_early_setup.c"
  66 #include "southbridge/amd/sb600/sb600_early_setup.c"
  67
  68 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  69 static void memreset(int controllers, const struct mem_controller *ctrl)
  70 {
  71 }
  72
  73 /* called in raminit_f.c */
  74 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  75 {
  76 }
  77
  78 /*called in raminit_f.c */
  79 static inline int spd_read_byte(u32 device, u32 address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84 #include "northbridge/amd/amdk8/amdk8.h"
  85 #include "northbridge/amd/amdk8/incoherent_ht.c"
  86 #include "northbridge/amd/amdk8/raminit.c"
  87 #include "northbridge/amd/amdk8/coherent_ht.c"
  88 #include "sdram/generic_sdram.c"
  89 #include "resourcemap.c"
  90
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93 #include "cpu/amd/car/copy_and_run.c"
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #include "cpu/amd/model_fxx/fidvid.c"
  99
 100 #if USE_FALLBACK_IMAGE == 1
 101
 102 #include "northbridge/amd/amdk8/early_ht.c"
 103
 104 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         /* Is this a cpu only reset? Is this a secondary cpu? */
 107         if ((cpu_init_detectedx) || (!boot_cpu())) {
 108                 if (last_boot_normal()) {       /* RTC already inited */
 109                         goto normal_image;
 110                 } else {
 111                         goto fallback_image;
 112                 }
 113         }
 114         /* Nothing special needs to be done to find bus 0 */
 115         /* Allow the HT devices to be found */
 116         enumerate_ht_chain();
 117
 118         sb600_lpc_port80();
 119         /* sb600_pci_port80(); */
 120
 121         /* Is this a deliberate reset by the bios */
 122         if (bios_reset_detected() && last_boot_normal()) {
 123                 goto normal_image;
 124         }
 125         /* This is the primary cpu how should I boot? */
 126         else if (do_normal_boot()) {
 127                 goto normal_image;
 128         } else {
 129                 goto fallback_image;
 130         }
 131       normal_image:
 132         post_code(0x01);
 133         __asm__ volatile ("jmp __normal_image": /* outputs */
 134                           :"a" (bist), "b"(cpu_init_detectedx));        /* inputs */
 135
 136       fallback_image:
 137         post_code(0x02);
 138 }
 139 #endif                          /* USE_FALLBACK_IMAGE == 1 */
 140
 141 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 142
 143 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 144 {
 145
 146 #if USE_FALLBACK_IMAGE == 1
 147         failover_process(bist, cpu_init_detectedx);
 148 #endif
 149         real_main(bist, cpu_init_detectedx);
 150 }
 151
 152 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 153 {
 154         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 155         int needs_reset = 0;
 156         u32 bsp_apicid = 0;
 157         msr_t msr;
 158         struct sys_info *sysinfo =
 159             (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
 160                                 DCACHE_RAM_GLOBAL_VAR_SIZE);
 161
 162         if (bist == 0) {
 163                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 164         }
 165
 166         enable_rs690_dev8();
 167         sb600_lpc_init();
 168
 169         /* Pistachio used a FPGA to enable serial debug instead of a SIO
 170          * and it doens't require any special setup. */
 171         uart_init();
 172         console_init();
 173
 174         post_code(0x03);
 175
 176         /* Halt if there was a built in self test failure */
 177         report_bist_failure(bist);
 178         printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
 179
 180         setup_pistachio_resource_map();
 181
 182         setup_coherent_ht_domain();
 183
 184 #if CONFIG_LOGICAL_CPUS==1
 185         /* It is said that we should start core1 after all core0 launched */
 186         wait_all_core0_started();
 187         start_other_cores();
 188 #endif
 189         wait_all_aps_started(bsp_apicid);
 190
 191         /* it will set up chains and store link pair for optimization later,
 192          * it will init sblnk and sbbusn, nodes, sbdn */
 193         ht_setup_chains_x(sysinfo);
 194
 195         /* run _early_setup before soft-reset. */
 196         rs690_early_setup();
 197         sb600_early_setup();
 198
 199         post_code(0x04);
 200
 201         msr = rdmsr(0xc0010042);
 202         printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 203
 204         enable_fid_change();
 205         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 206         init_fidvid_bsp(bsp_apicid);
 207
 208         // show final fid and vid
 209         msr = rdmsr(0xc0010042);
 210         printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 211
 212         post_code(0x05);
 213
 214         needs_reset = optimize_link_coherent_ht();
 215         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 216         rs690_htinit();
 217         printk_debug("needs_reset=0x%x\n", needs_reset);
 218
 219         post_code(0x06);
 220
 221         if (needs_reset) {
 222                 print_info("ht reset -\r\n");
 223                 soft_reset();
 224         }
 225
 226         allow_all_aps_stop(bsp_apicid);
 227
 228         /* It's the time to set ctrl now; */
 229         printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 230                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 231         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 232
 233         post_code(0x07);
 234
 235         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 236
 237         post_code(0x08);
 238
 239         rs690_before_pci_init();
 240         sb600_before_pci_init();
 241
 242         post_cache_as_ram();
 243 }