Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings.
[coreboot.git] / src / mainboard / amd / pistachio / Kconfig
1 if BOARD_AMD_PISTACHIO
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_AM2
7         select DIMM_DDR2
8         select NORTHBRIDGE_AMD_AMDK8
9         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
10         select SOUTHBRIDGE_AMD_RS690
11         select SOUTHBRIDGE_AMD_SB600
12         select BOARD_HAS_FADT
13         select HAVE_BUS_CONFIG
14         select HAVE_OPTION_TABLE
15         select HAVE_PIRQ_TABLE
16         select HAVE_MP_TABLE
17         select CACHE_AS_RAM
18         select HAVE_HARD_RESET
19         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
20         select WAIT_BEFORE_CPUS_INIT
21         select HAVE_ACPI_TABLES
22         select BOARD_ROMSIZE_KB_1024
23
24 config MAINBOARD_DIR
25         string
26         default amd/pistachio
27
28 config DCACHE_RAM_BASE
29         hex
30         default 0xc8000
31
32 config DCACHE_RAM_SIZE
33         hex
34         default 0x08000
35
36 config DCACHE_RAM_GLOBAL_VAR_SIZE
37         hex
38         default 0x01000
39
40 config APIC_ID_OFFSET
41         hex
42         default 0x0
43
44 config MAINBOARD_PART_NUMBER
45         string
46         default "Pistachio"
47
48 config MAX_CPUS
49         int
50         default 2
51
52 config MAX_PHYSICAL_CPUS
53         int
54         default 1
55
56 config SB_HT_CHAIN_ON_BUS0
57         int
58         default 1
59
60 config HT_CHAIN_END_UNITID_BASE
61         hex
62         default 0x1
63
64 config HT_CHAIN_UNITID_BASE
65         hex
66         default 0x0
67
68 config IRQ_SLOT_COUNT
69         int
70         default 11
71
72 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
73         hex
74         default 0x1022
75
76 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
77         hex
78         default 0x3050
79
80 endif # BOARD_AMD_PISTACHIO