2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 ## Compute the location and size of where this firmware image
25 ## (coreboot plus bootloader) will live in the boot rom chip.
28 default ROM_SECTION_SIZE = FALLBACK_SIZE
29 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
31 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
32 default ROM_SECTION_OFFSET = 0
36 ## Compute the start location and size size of
37 ## The coreboot bootloader.
39 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
40 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
43 ## Compute where this copy of coreboot will start in the boot rom
45 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
48 ## Compute a range of ROM that can cached to speed up coreboot,
51 ## XIP_ROM_SIZE must be a power of 2.
52 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
54 default XIP_ROM_SIZE=65536
55 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
60 ## Build the objects we have code for in this directory.
67 if HAVE_MP_TABLE object mptable.o end
77 depends "$(MAINBOARD)/acpi/*.asl"
78 action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
79 action "mv dsdt.hex dsdt.c"
90 makerule ./cache_as_ram_auto.o
91 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
92 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
97 makerule ./cache_as_ram_auto.inc
98 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
99 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
100 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
101 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
108 ## Build our 16 bit and 32 bit coreboot entry code
110 mainboardinit cpu/x86/16bit/entry16.inc
111 mainboardinit cpu/x86/32bit/entry32.inc
112 ldscript /cpu/x86/16bit/entry16.lds
115 ldscript /cpu/x86/32bit/entry32.lds
119 ldscript /cpu/amd/car/cache_as_ram.lds
124 ## Build our reset vector (This is where coreboot is entered)
126 if USE_FALLBACK_IMAGE
127 mainboardinit cpu/x86/16bit/reset16.inc
128 ldscript /cpu/x86/16bit/reset16.lds
130 mainboardinit cpu/x86/32bit/reset32.inc
131 ldscript /cpu/x86/32bit/reset32.lds
135 ## Include an id string (For safe flashing)
137 mainboardinit arch/i386/lib/id.inc
138 ldscript /arch/i386/lib/id.lds
142 ## Setup Cache-As-Ram
144 mainboardinit cpu/amd/car/cache_as_ram.inc
148 ### This is the early phase of coreboot startup
149 ### Things are delicate and we test to see if we should
150 ### failover to another image.
152 if USE_FALLBACK_IMAGE
154 ldscript /arch/i386/lib/failover.lds
156 ldscript /arch/i386/lib/failover.lds
157 mainboardinit ./failover.inc
162 ### O.k. We aren't just an intermediary anymore!
171 initobject cache_as_ram_auto.o
173 mainboardinit ./cache_as_ram_auto.inc
179 ## Include the secondary Configuration files
185 #The variables belong to mainboard are defined here.
187 #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
188 #Define vga_rom_address = 0xfff0000
189 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
190 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
191 # 1: the system allows a PCIE link to be established on Dev2 or Dev3.
192 #Define gfx_dual_slot, 0: single slot, 1: dual slot
193 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
194 #Define gfx_tmds, 0: didn't support TMDS, 1: support
195 #Define gfx_compliance, 0: didn't support compliance, 1: support
196 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
197 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
198 chip northbridge/amd/amdk8/root_complex
199 device apic_cluster 0 on
200 chip cpu/amd/socket_AM2
204 device pci_domain 0 on
205 chip northbridge/amd/amdk8
206 device pci 18.0 on # southbridge, K8 HT Configuration
207 chip southbridge/amd/rs690
208 device pci 0.0 on end # HT 0x7910
209 # device pci 0.1 off end # CLK
210 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
211 chip drivers/pci/onboard
212 device pci 5.0 on end # Internal Graphics 0x791F
213 register "rom_address" = "0xfff00000"
216 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
217 device pci 3.0 off end # PCIE P2P bridge 0x791b
218 device pci 4.0 on end # PCIE P2P bridge 0x7914
219 device pci 5.0 on end # PCIE P2P bridge 0x7915
220 device pci 6.0 on end # PCIE P2P bridge 0x7916
221 device pci 7.0 on end # PCIE P2P bridge 0x7917
222 device pci 8.0 off end # NB/SB Link P2P bridge
223 register "vga_rom_address" = "0xfff00000"
224 register "gpp_configuration" = "4"
225 register "port_enable" = "0xfc"
226 register "gfx_dev2_dev3" = "1"
227 register "gfx_dual_slot" = "0"
228 register "gfx_lane_reversal" = "0"
229 register "gfx_tmds" = "0"
230 register "gfx_compliance" = "0"
231 register "gfx_reconfiguration" = "1"
232 register "gfx_link_width" = "0"
234 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
235 device pci 12.0 on end # SATA 0x4380
236 device pci 13.0 on end # USB 0x4387
237 device pci 13.1 on end # USB 0x4388
238 device pci 13.2 on end # USB 0x4389
239 device pci 13.3 on end # USB 0x438a
240 device pci 13.4 on end # USB 0x438b
241 device pci 13.5 on end # USB 2 0x4386
242 device pci 14.0 on # SM 0x4385
243 chip drivers/generic/generic #dimm 0-0-0
246 chip drivers/generic/generic #dimm 0-0-1
247 device i2c 51 off end
249 chip drivers/generic/generic #dimm 0-1-0
250 device i2c 52 off end
252 chip drivers/generic/generic #dimm 0-1-1
253 device i2c 53 off end
256 device pci 14.1 on end # IDE 0x438c
257 device pci 14.2 on end # HDA 0x4383
258 device pci 14.3 on end # LPC 0x438d
259 device pci 14.4 on end # PCI 0x4384
260 device pci 14.5 on end # ACI 0x4382
261 device pci 14.6 on end # MCI 0x438e
262 register "ide0_enable" = "1"
263 register "sata0_enable" = "1"
264 register "hda_viddid" = "0x10ec0882"
265 end #southbridge/amd/sb600
266 end # device pci 18.0
268 device pci 18.1 on end # K8 Address Map
269 device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
270 device pci 18.3 on end # K8 Miscellaneous Control
271 end #northbridge/amd/amdk8
273 end #northbridge/amd/amdk8/root_complex