2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
23 #include <cpu/x86/msr.h>
24 #include <cpu/amd/lxdef.h>
25 #include <device/pci_def.h>
26 #include "../../../southbridge/amd/cs5536/cs5536.h"
29 /* Print the platform configuration - do before PCI init or it will not work right */
32 #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
37 int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
38 CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
39 CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF,
41 CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
44 int gliu0_msr_defs[] =
45 { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4,
46 MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
47 GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
48 GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
50 GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
51 GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3,
52 GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
53 GLIU0_GLD_MSR_COH, GL_END
56 int gliu1_msr_defs[] =
57 { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3,
58 MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
59 MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9,
61 GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3,
63 GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
64 GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
65 GLIU1_GLD_MSR_COH, GL_END
69 { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
70 CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
74 { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO,
76 MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
80 { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF,
82 GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR,
88 { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3,
90 MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
94 printk_debug("---------- CPU ------------\n");
96 for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
97 msr = rdmsr(cpu_msr_defs[i]);
98 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
99 cpu_msr_defs[i], msr.hi, msr.lo);
102 printk_debug("---------- GLIU 0 ------------\n");
104 for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
105 msr = rdmsr(gliu0_msr_defs[i]);
106 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
107 gliu0_msr_defs[i], msr.hi, msr.lo);
110 printk_debug("---------- GLIU 1 ------------\n");
112 for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
113 msr = rdmsr(gliu1_msr_defs[i]);
114 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
115 gliu1_msr_defs[i], msr.hi, msr.lo);
118 printk_debug("---------- RCONF ------------\n");
120 for (i = 0; rconf_msr[i] != GL_END; i++) {
121 msr = rdmsr(rconf_msr[i]);
122 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
126 printk_debug("---------- VARIA ------------\n");
127 msr = rdmsr(0x51300010);
128 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
131 msr = rdmsr(0x51400015);
132 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
135 printk_debug("---------- DIVIL IRQ ------------\n");
136 msr = rdmsr(MDD_IRQM_YLOW);
137 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
139 msr = rdmsr(MDD_IRQM_YHIGH);
140 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
142 msr = rdmsr(MDD_IRQM_ZLOW);
143 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
145 msr = rdmsr(MDD_IRQM_ZHIGH);
146 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
149 printk_debug("---------- PCI ------------\n");
151 for (i = 0; pci_msr[i] != GL_END; i++) {
152 msr = rdmsr(pci_msr[i]);
153 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
157 printk_debug("---------- LPC/UART DMA ------------\n");
159 for (i = 0; dma_msr[i] != GL_END; i++) {
160 msr = rdmsr(dma_msr[i]);
161 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
165 printk_debug("---------- CS5536 ------------\n");
167 for (i = 0; cs5536_msr[i] != GL_END; i++) {
168 msr = rdmsr(cs5536_msr[i]);
169 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
173 iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
174 printk_debug("IOR 0x%08X is now 0x%08X\n",
175 GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
176 iol = inl(GPIOL_EVENTS_ENABLE);
177 printk_debug("IOR 0x%08X is now 0x%08X\n",
178 GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
179 iol = inl(GPIOL_INPUT_INVERT_ENABLE);
180 printk_debug("IOR 0x%08X is now 0x%08X\n",
181 GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
182 iol = inl(GPIO_MAPPER_X);
183 printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
185 #endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
188 static void init(struct device *dev)
190 printk_debug("Norwich ENTER %s\n", __FUNCTION__);
191 printk_debug("Norwich EXIT %s\n", __FUNCTION__);
194 static void enable_dev(struct device *dev)
196 dev->ops->init = init;
199 struct chip_operations mainboard_amd_norwich_ops = {
200 CHIP_NAME("AMD Norwich Mainboard")
201 .enable_dev = enable_dev,