2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/pci_def.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
29 #include "pc80/serial.c"
30 #include "arch/i386/lib/console.c"
31 #include "ram/ramtest.c"
32 #include "cpu/x86/bist.h"
33 #include "cpu/x86/msr.h"
34 #include <cpu/amd/lxdef.h>
35 #include <cpu/amd/geode_post_code.h>
36 #include "southbridge/amd/cs5536/cs5536.h"
38 #define POST_CODE(x) outb(x, 0x80)
40 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
41 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
43 static inline int spd_read_byte(unsigned device, unsigned address)
45 return smbus_read_byte(device, address);
48 #define ManualConf 0 /* Do automatic strapped PLL config */
49 #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
50 #define PLLMSRlo 0x02000030
53 #include "northbridge/amd/lx/raminit.h"
54 #include "northbridge/amd/lx/pll_reset.c"
55 #include "northbridge/amd/lx/raminit.c"
56 #include "sdram/generic_sdram.c"
57 #include "cpu/amd/model_lx/cpureginit.c"
58 #include "cpu/amd/model_lx/syspreinit.c"
60 static void msr_init(void)
62 /* Setup access to the MC for low memory. Note MC not setup yet. */
63 __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02);
65 __builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000);
66 __builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000);
68 __builtin_wrmsr(MSR_GLIU1 + 0x20, 0xfff80, 0x20000000);
69 __builtin_wrmsr(MSR_GLIU1 + 0x21, 0x80fffe0, 0x20000000);
72 static void mb_gpio_init(void)
74 /* Early mainboard specific GPIO setup */
77 static void main(unsigned long bist)
79 static const struct mem_controller memctrl[] = {
80 {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
88 /* NOTE: must do this AFTER the early_setup!
89 * it is counting on some early MSR setup
92 /* cs5536_disable_internal_uart disable them for now, set them up later... */
93 cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
98 pll_reset(ManualConf);
102 sdram_initialize(1, memctrl);
104 /* Check all of memory */
105 //ram_check(0x00000000, 640*1024);