2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The coreboot bootloader.
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
22 ## Compute where this copy of coreboot will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up coreboot,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Set all of the defaults for an x86 architecture
44 ## Build the objects we have code for in this directory.
56 #compile cache_as_ram.c to auto.inc
57 makerule ./cache_as_ram_auto.inc
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
60 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
61 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
67 ## Build our 16 bit and 32 bit coreboot entry code
69 mainboardinit cpu/x86/16bit/entry16.inc
70 mainboardinit cpu/x86/32bit/entry32.inc
71 ldscript /cpu/x86/16bit/entry16.lds
72 ldscript /cpu/x86/32bit/entry32.lds
75 ## Build our reset vector (This is where coreboot is entered)
78 mainboardinit cpu/x86/16bit/reset16.inc
79 ldscript /cpu/x86/16bit/reset16.lds
81 mainboardinit cpu/x86/32bit/reset32.inc
82 ldscript /cpu/x86/32bit/reset32.lds
85 ### Should this be in the northbridge code?
86 #not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
89 ## Include an id string (For safe flashing)
91 mainboardinit arch/i386/lib/id.inc
92 ldscript /arch/i386/lib/id.lds
95 ### This is the early phase of coreboot startup
96 ### Things are delicate and we test to see if we should
97 ### failover to another image.
100 ldscript /arch/i386/lib/failover.lds
101 # mainboardinit ./failover.inc
105 ### O.k. We aren't just an intermediary anymore!
111 mainboardinit cpu/x86/fpu/enable_fpu.inc
114 mainboardinit cpu/amd/model_lx/cache_as_ram.inc
115 mainboardinit ./cache_as_ram_auto.inc
119 ## Include the secondary Configuration files
124 chip northbridge/amd/lx
125 device pci_domain 0 on
126 device pci 1.0 on end # Northbridge
127 device pci 1.1 on end # Graphics
128 chip southbridge/amd/cs5536
129 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
130 # SIRQ Mode = Active(Quiet) mode. Save power....
131 # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
132 register "lpc_serirq_enable" = "0x00001002"
133 register "lpc_serirq_polarity" = "0x0000EFFD"
134 register "lpc_serirq_mode" = "1"
135 register "enable_gpio_int_route" = "0x0D0C0700"
136 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
137 register "enable_USBP4_device" = "0" #0: host, 1:device
138 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
139 register "com1_enable" = "1"
140 register "com1_address" = "0x3F8"
141 register "com1_irq" = "4"
142 register "com2_enable" = "1"
143 register "com2_address" = "0x2F8"
144 register "com2_irq" = "3"
145 register "unwanted_vpci[0]" = "0" # End of list has a zero
146 device pci b.0 on end # Slot 3
147 device pci c.0 on end # Slot 4
148 device pci d.0 on end # Slot 1
149 device pci e.0 on end # Slot 2
150 device pci f.0 on end # ISA Bridge
151 device pci f.2 on end # IDE Controller
152 device pci f.3 on end # Audio
153 device pci f.4 on end # OHCI
154 device pci f.5 on end # EHCI
157 # APIC cluster is late CPU init.
158 device apic_cluster 0 on
159 chip cpu/amd/model_lx