2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
27 #include <cpu/amd/amdk8_sysconf.h>
30 extern u8 bus_rs780[11];
31 extern u8 bus_sb700[2];
33 extern u32 apicid_sb700;
35 extern u32 bus_type[256];
36 extern u32 sbdn_rs780;
37 extern u32 sbdn_sb700;
39 static void *smp_write_config_table(void *v)
41 struct mp_config_table *mc;
44 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 mptable_init(mc, "MAHOGANY ", LAPIC_ADDR);
48 smp_write_processors(mc);
52 /* Bus: Bus ID Type */
53 /* define bus and isa numbers */
54 for (j = 0; j < bus_isa; j++) {
55 smp_write_bus(mc, j, (char *)"PCI ");
57 smp_write_bus(mc, bus_isa, (char *)"ISA ");
59 /* I/O APICs: APIC ID Version State Address */
66 dev_find_slot(bus_sb700[0],
67 PCI_DEVFN(sbdn_sb700 + 0x14, 0));
69 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
70 smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
72 /* Initialize interrupt mapping */
74 byte = pci_read_config8(dev, 0x63);
76 byte |= 0; /* 0: INTA, ...., 7: INTH */
77 pci_write_config8(dev, 0x63, byte);
80 dword = pci_read_config32(dev, 0xac);
82 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
83 /* dword |= 1<<22; PIC and APIC co exists */
84 pci_write_config32(dev, 0xac, dword);
87 * 00:12.0: PROG SATA : INT F
95 * 00:14.2: Prog HDA : INT E
102 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
103 #define IO_LOCAL_INT(type, intr, apicid, pin) \
104 smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
106 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
108 /* PCI interrupts are level triggered, and are
109 * associated with a specific bus/device/function tuple.
111 #if CONFIG_GENERATE_ACPI_TABLES == 0
112 #define PCI_INT(bus, dev, fn, pin) \
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
115 #define PCI_INT(bus, dev, fn, pin)
119 PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
120 PCI_INT(0x0, 0x12, 0x1, 0x11);
121 PCI_INT(0x0, 0x13, 0x0, 0x12);
122 PCI_INT(0x0, 0x13, 0x1, 0x13);
123 PCI_INT(0x0, 0x14, 0x0, 0x10);
126 PCI_INT(0x0, 0x11, 0x0, 0x16);
128 /* HD Audio: b0:d20:f1:reg63 should be 0. */
129 /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
131 /* on board NIC & Slot PCIE. */
132 /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
133 /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
134 PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
135 /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
136 PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
137 /* configuration B doesnt need dev 5,6,7 */
139 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
140 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
141 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
143 PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
144 PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
148 PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
149 PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
150 PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
151 PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
154 PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
155 PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
156 PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
157 PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
160 PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
161 PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
162 PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
163 PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
165 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
166 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
167 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
168 /* There is no extension information... */
170 /* Compute the checksums */
172 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
173 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
174 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
175 mc, smp_next_mpe_entry(mc));
176 return smp_next_mpe_entry(mc);
179 unsigned long write_smp_table(unsigned long addr)
182 v = smp_write_floating_table(addr);
183 return (unsigned long)smp_write_config_table(v);