2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * AMD User options selection for a Sabine/Lynx platform solution system
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
28 * For Information about this file, see @ref platforminstall.
30 * @xrefitem bom "File Content Label" "Release Content"
32 * @e sub-project: Core
33 * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
36 #include "CommonReturns.h"
38 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
41 /* Select the cpu family. */
44 /* Select the cpu socket type. */
45 #define INSTALL_G34_SOCKET_SUPPORT TURE
46 #define INSTALL_C32_SOCKET_SUPPORT FALSE
47 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
48 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
49 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
50 #define INSTALL_FS1_SOCKET_SUPPORT FALSE
51 #define INSTALL_FM1_SOCKET_SUPPORT FALSE
52 #define INSTALL_FP1_SOCKET_SUPPORT FALSE
53 #define INSTALL_FT1_SOCKET_SUPPORT FALSE
54 #define INSTALL_AM3_SOCKET_SUPPORT FALSE
57 * Agesa optional capabilities selection.
58 * Uncomment and mark FALSE those features you wish to include in the build.
59 * Comment out or mark TRUE those features you want to REMOVE from the build.
62 /* User makes option selections here
63 * Comment out the items wanted to be included in the build.
64 * Uncomment those items you with to REMOVE from the build.
66 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
67 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
68 //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
69 //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
70 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
71 //#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
72 #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
73 //#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
74 //#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE
75 //#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
76 //#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
77 //#define BLDOPT_REMOVE_SRAT TRUE
78 //#define BLDOPT_REMOVE_SLIT TRUE
79 #define BLDOPT_REMOVE_WHEA TRUE
80 //#define BLDOPT_REMOVE_DMI TRUE
81 #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
82 //#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
83 /* Build configuration values here.
85 #define BLDCFG_VRM_CURRENT_LIMIT 120000
86 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
87 #define BLDCFG_PLAT_NUM_IO_APICS 2
88 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
89 #define BLDCFG_MEM_INIT_PSTATE 0
90 #define BLDCFG_AMD_PSTATE_CAP_VALUE 0
92 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
94 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
95 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
96 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
97 #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
98 #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
99 #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
100 #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
101 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
102 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE
103 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
104 #define BLDCFG_MEMORY_POWER_DOWN TRUE
105 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE
106 #define BLDCFG_ONLINE_SPARE TRUE
107 #define BLDCFG_MEMORY_PARITY_ENABLE TRUE
108 #define BLDCFG_BANK_SWIZZLE TRUE
109 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
110 #define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
111 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
112 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
113 #define BLDCFG_USE_BURST_MODE FALSE
114 #define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE
115 #define BLDCFG_ENABLE_ECC_FEATURE TRUE
116 #define BLDCFG_ECC_REDIRECTION TRUE
117 #define BLDCFG_SCRUB_IC_RATE 0
118 #define BLDCFG_ECC_SYNC_FLOOD TRUE
119 #define BLDCFG_ECC_SYMBOL_SIZE 0
120 #define BLDCFG_1GB_ALIGN FALSE
121 #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
122 #define BLDCFG_PLATFORM_C1E_OPDATA 0x2000
123 //#define BLDCFG_USE_ATM_MODE TRUE
125 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
126 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0
127 #define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife
128 //#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e
129 //#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000
131 //#define IDSOPT_IDS_ENABLED TRUE
132 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
133 #define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
134 #define BLDCFG_PSTATE_HPC_MODE FALSE
136 #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
138 * Agesa entry points used in this implementation.
140 /* Process the options...
141 * This file include MUST occur AFTER the user option selection settings
143 #define AGESA_ENTRY_INIT_RESET TRUE//FALSE
144 #define AGESA_ENTRY_INIT_RECOVERY FALSE
145 #define AGESA_ENTRY_INIT_EARLY TRUE
146 #define AGESA_ENTRY_INIT_POST TRUE
147 #define AGESA_ENTRY_INIT_ENV TRUE
148 #define AGESA_ENTRY_INIT_MID TRUE
149 #define AGESA_ENTRY_INIT_LATE TRUE
150 #define AGESA_ENTRY_INIT_S3SAVE TRUE
151 #define AGESA_ENTRY_INIT_RESUME TRUE
152 #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
153 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
154 #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
157 /*****************************************************************************
158 * Define the RELEASE VERSION string
160 * The Release Version string should identify the next planned release.
161 * When a branch is made in preparation for a release, the release manager
162 * should change/confirm that the branch version of this file contains the
163 * string matching the desired version for the release. The trunk version of
164 * the file should always contain a trailing 'X'. This will make sure that a
165 * development build from trunk will not be confused for a released version.
166 * The release manager will need to remove the trailing 'X' and update the
167 * version string as appropriate for the release. The trunk copy of this file
168 * should also be updated/incremented for the next expected version, + trailing 'X'
169 ****************************************************************************/
170 // This is the delivery package title, "MarG34PI"
171 // This string MUST be exactly 8 characters long
172 #define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
174 // This is the release version number of the AGESA component
175 // This string MUST be exactly 12 characters long
176 #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '}
178 // The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
179 #define INSTALL_G34_SOCKET_SUPPORT TRUE
180 #define INSTALL_FAMILY_10_SUPPORT TRUE
181 #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
183 #ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
184 #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
185 #undef INSTALL_FAMILY_10_SUPPORT
186 #define INSTALL_FAMILY_10_SUPPORT FALSE
190 #ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
191 #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
192 #undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
193 #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE
197 // The following definitions specify the default values for various parameters in which there are
198 // no clearly defined defaults to be used in the common file. The values below are based on product
199 // and BKDG content, please consult the AGESA Memory team for consultation.
200 #define DFLT_SCRUB_DRAM_RATE (0xFF)
201 #define DFLT_SCRUB_L2_RATE (0x10)
202 #define DFLT_SCRUB_L3_RATE (0x10)
203 #define DFLT_SCRUB_IC_RATE (0)
204 #define DFLT_SCRUB_DC_RATE (0x12)
205 #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
206 #define DFLT_VRM_SLEW_RATE (2500)
208 /* Process the options...
209 * This file include MUST occur
210 AFTER the user option selection settings
212 CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
214 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
216 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
217 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
218 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
219 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
220 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
222 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
223 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
227 #define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList
229 // And another platform specific one ...
230 //CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] =
232 // HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
233 // HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
237 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] =
239 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
240 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
241 HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK,
242 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
246 #define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList
248 // A performance-per-watt optimization.
249 CONST SKIP_REGANG ROMDATA PerfPerWatt[] = {
250 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF,
251 HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF,
255 // uncomment the line below to make Perf-per-watt enabled by default.
256 #define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt
259 CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] =
261 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
265 #define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList
267 CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] =
269 // Source Socket, Link (4-7 are sublink 1), Target Socket
278 #define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap
281 * PCI Bus numbers for Drachma/Peso board
283 CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] =
285 // Socket, Link, SecBus, SubBus
286 0, 2, 0x00, 0xBF, // RD890 of Dinar
287 1, 0, 0xC0, 0xFF, // HTX
291 #define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers
293 CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] =
295 { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone},
296 { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3},
297 { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6},
301 #define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList
303 CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] =
305 // {socketA, linkA, socketB, linkB}
309 #define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap
313 * Device Capabilities Override for disabling ID Clumping
315 CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
317 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
318 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0},
322 #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
325 #include "cpuRegisters.h"
326 #include "cpuFamRegisters.h"
327 #include "cpuFamilyTranslation.h"
328 #include "AdvancedApi.h"
329 #include "heapManager.h"
330 #include "CreateStruct.h"
331 #include "cpuFeatures.h"
333 #include "CommonReturns.h"
334 #include "cpuEarlyInit.h"
335 #include "cpuLateInit.h"
336 #include "GnbInterfaceStub.h"
337 #include "PlatformInstall.h"
339 /*----------------------------------------------------------------------------------------
340 * CUSTOMER OVERIDES MEMORY TABLE
341 *----------------------------------------------------------------------------------------
345 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
346 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
347 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
348 * use its default conservative settings.
350 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
352 // The following macros are supported (use comma to separate macros):
354 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
355 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
356 // AGESA will base on this value to disable unused MemClk to save power.
358 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
359 // Bit AM3/S1g3 pin name
360 // 0 M[B,A]_CLK_H/L[0]
361 // 1 M[B,A]_CLK_H/L[1]
362 // 2 M[B,A]_CLK_H/L[2]
363 // 3 M[B,A]_CLK_H/L[3]
364 // 4 M[B,A]_CLK_H/L[4]
365 // 5 M[B,A]_CLK_H/L[5]
366 // 6 M[B,A]_CLK_H/L[6]
367 // 7 M[B,A]_CLK_H/L[7]
368 // And platform has the following routing:
369 // CS0 M[B,A]_CLK_H/L[4]
370 // CS1 M[B,A]_CLK_H/L[2]
371 // CS2 M[B,A]_CLK_H/L[3]
372 // CS3 M[B,A]_CLK_H/L[5]
373 // Then platform can specify the following macro:
374 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
376 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
377 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
378 // AGESA will base on this value to tristate unused CKE to save power.
380 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
381 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
382 // AGESA will base on this value to tristate unused ODT pins to save power.
384 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
385 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
386 // AGESA will base on this value to tristate unused Chip select to save power.
388 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
389 // Specifies the number of DIMM slots per channel.
391 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
392 // Specifies the number of channels per socket.
395 // Dinar has the following routing:
396 // CS0 M[B,A]_CLK_H/L[0]
397 // CS1 M[B,A]_CLK_H/L[2]
398 // CS2 M[B,A]_CLK_H/L[1]
399 // CS3 M[B,A]_CLK_H/L[3]
400 MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
401 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
406 * These tables are optional and may be used to adjust memory timing settings
412 UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] =
414 // Hardcoded Memory Training Values
416 // The following macro should be used to override training values for your platform
418 // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
421 // The following training hardcode values are example values that were taken from a tilapia motherboard
422 // with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in
423 // the table and replace the byte lane values with your own.
425 // ------------------ BYTE LANES ----------------------
426 // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
428 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
429 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
430 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
431 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
433 // DQS Receiver Enable
434 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
435 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
436 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
437 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
440 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
441 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
442 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
443 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
446 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
447 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
448 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
449 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
450 //--------------------------------------------------------------------------------------------------------------------------------------------------
452 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
454 UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
455 /* ***************************************************************************
456 * Optional User code to be included into the AGESA build
457 * These may be 32-bit call-out routines...
462 // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
465 // /* platform code to read an SPD... */
469 /* ***************************************************************************
470 * Optional User code to be included into the AGESA build
471 * These may be 32-bit call-out routines...
476 // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
479 // /* platform code to read an SPD... */