2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /*----------------------------------------------------------------------------------------
21 * M O D U L E S U S E D
22 *----------------------------------------------------------------------------------------
26 #ifndef _AGESAWRAPPER_H_
27 #define _AGESAWRAPPER_H_
33 /*----------------------------------------------------------------------------------------
34 * D E F I N I T I O N S A N D M A C R O S
35 *----------------------------------------------------------------------------------------
37 /* Define AMD Ontario APPU SSID/SVID */
38 #define AMD_APU_SVID 0x1022
39 #define AMD_APU_SSID 0x1234
40 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
41 #define MMIO_NP_BIT BIT7
43 /* Hudson-2 ACPI PmIO Space Define */
44 #define SB_ACPI_BASE_ADDRESS 0x0400
45 #define ACPI_MMIO_BASE 0xFED80000
46 #define SB_CFG_BASE 0x000 // DWORD
47 #define GPIO_BASE 0x100 // BYTE
48 #define SMI_BASE 0x200 // DWORD
49 #define PMIO_BASE 0x300 // DWORD
50 #define PMIO2_BASE 0x400 // BYTE
51 #define BIOS_RAM_BASE 0x500 // BYTE
52 #define CMOS_RAM_BASE 0x600 // BYTE
53 #define CMOS_BASE 0x700 // BYTE
54 #define ASF_BASE 0x900 // DWORD
55 #define SMBUS_BASE 0xA00 // DWORD
56 #define WATCHDOG_BASE 0xB00 // ??
57 #define HPET_BASE 0xC00 // DWORD
58 #define IOMUX_BASE 0xD00 // BYTE
59 #define MISC_BASE 0xE00
60 #define SERIAL_DEBUG_BASE 0x1000
61 #define GFX_DAC_BASE 0x1400
62 #define CEC_BASE 0x1800
63 #define XHCI_BASE 0x1C00
64 #define ACPI_SMI_DATA_PORT 0xB1
65 #define R_SB_ACPI_PM1_STATUS 0x00
66 #define R_SB_ACPI_PM1_ENABLE 0x02
67 #define R_SB_ACPI_PM_CONTROL 0x04
68 #define R_SB_ACPI_EVENT_STATUS 0x20
69 #define R_SB_ACPI_EVENT_ENABLE 0x24
70 #define B_PWR_BTN_STATUS BIT8
71 #define B_WAKEUP_STATUS BIT15
73 #define SB_PM_INDEX_PORT 0xCD6
74 #define SB_PM_DATA_PORT 0xCD7
75 #define SB_PMIOA_REG24 0x24 // AcpiMmioEn
76 #define MmioAddress( BaseAddr, Register ) \
80 #define Mmio32Ptr( BaseAddr, Register ) \
81 ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
82 #define Mmio32( BaseAddr, Register ) \
83 *Mmio32Ptr( BaseAddr, Register )
86 PICK_DMI, /* DMI Interface */
87 PICK_PSTATE, /* Acpi Pstate SSDT Table */
88 PICK_SRAT, /* SRAT Table */
89 PICK_SLIT, /* SLIT Table */
90 PICK_WHEA_MCE, /* WHEA MCE table */
91 PICK_WHEA_CMC, /* WHEA CMV table */
92 PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
97 /*----------------------------------------------------------------------------------------
98 * T Y P E D E F S A N D S T R U C T U R E S
99 *----------------------------------------------------------------------------------------
104 AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
105 } BIOS_CALLOUT_STRUCT;
107 /*----------------------------------------------------------------------------------------
108 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
109 *----------------------------------------------------------------------------------------
112 /*----------------------------------------------------------------------------------------
113 * E X P O R T E D F U N C T I O N S
114 *----------------------------------------------------------------------------------------
117 /*---------------------------------------------------------------------------------------
118 * L O C A L F U N C T I O N S
119 *---------------------------------------------------------------------------------------
122 //void brazos_platform_stage(void);
123 UINT32 agesawrapper_amdinitreset (void);
124 UINT32 agesawrapper_amdinitearly (void);
125 UINT32 agesawrapper_amdinitenv (void);
126 UINT32 agesawrapper_amdinitlate (void);
127 UINT32 agesawrapper_amdinitpost (void);
128 UINT32 agesawrapper_amdinitmid (void);
129 void sb_After_Pci_Init (void);
130 void sb_Mid_Post_Init (void);
131 void sb_Late_Post (void);
132 UINT32 agesawrapper_amdreadeventlog (void);
133 UINT32 agesawrapper_amdinitmmio (void);
134 void *agesawrapper_getlateinitptr (int pick);