2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #define RAMINIT_SYSINFO 1
24 #define K8_SET_FIDVID 1
25 #define QRANK_DIMM_SUPPORT 1
26 #if CONFIG_LOGICAL_CPUS==1
27 #define SET_NB_CFG_54 1
36 #define ICS951462_ADDRESS 0x69
37 #define SMBUS_HUB 0x71
41 #include <device/pci_def.h>
43 #include <device/pnp_def.h>
44 #include <arch/romcc_io.h>
45 #include <cpu/x86/lapic.h>
46 #include "option_table.h"
47 #include "pc80/mc146818rtc_early.c"
48 #include "pc80/serial.c"
49 #include "arch/i386/lib/console.c"
51 #define post_code(x) outb(x, 0x80)
53 #include <cpu/amd/model_fxx_rev.h>
54 #include "northbridge/amd/amdk8/raminit.h"
55 #include "cpu/amd/model_fxx/apic_timer.c"
56 #include "lib/delay.c"
58 #include "cpu/x86/lapic/boot_cpu.c"
59 #include "northbridge/amd/amdk8/reset_test.c"
60 #include "superio/ite/it8712f/it8712f_early_serial.c"
62 #include "cpu/amd/mtrr/amd_earlymtrr.c"
63 #include "cpu/x86/bist.h"
65 #include "northbridge/amd/amdk8/setup_resource_map.c"
67 #include "southbridge/amd/rs690/rs690_early_setup.c"
68 #include "southbridge/amd/sb600/sb600_early_setup.c"
69 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
71 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
72 static void memreset(int controllers, const struct mem_controller *ctrl)
76 /* called in raminit_f.c */
77 static inline void activate_spd_rom(const struct mem_controller *ctrl)
81 /*called in raminit_f.c */
82 static inline int spd_read_byte(u32 device, u32 address)
84 return smbus_read_byte(device, address);
87 #include "northbridge/amd/amdk8/amdk8.h"
88 #include "northbridge/amd/amdk8/incoherent_ht.c"
89 #include "northbridge/amd/amdk8/raminit_f.c"
90 #include "northbridge/amd/amdk8/coherent_ht.c"
91 #include "lib/generic_sdram.c"
92 #include "resourcemap.c"
94 #include "cpu/amd/dualcore/dualcore.c"
96 #include "cpu/amd/car/copy_and_run.c"
97 #include "cpu/amd/car/post_cache_as_ram.c"
99 #include "cpu/amd/model_fxx/init_cpus.c"
101 #include "cpu/amd/model_fxx/fidvid.c"
103 #include "northbridge/amd/amdk8/early_ht.c"
105 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
107 static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
111 struct cpuid_result cpuid1;
112 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
114 if (!cpu_init_detectedx && boot_cpu()) {
115 /* Nothing special needs to be done to find bus 0 */
116 /* Allow the HT devices to be found */
117 enumerate_ht_chain();
119 /* sb600_lpc_port80(); */
124 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
130 /* it8712f_enable_serial does not use its 1st parameter. */
131 it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
135 /* Halt if there was a built in self test failure */
136 report_bist_failure(bist);
137 printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
139 setup_dbm690t_resource_map();
141 setup_coherent_ht_domain();
143 #if CONFIG_LOGICAL_CPUS==1
144 /* It is said that we should start core1 after all core0 launched */
145 wait_all_core0_started();
148 wait_all_aps_started(bsp_apicid);
150 ht_setup_chains_x(sysinfo);
152 /* run _early_setup before soft-reset. */
156 /* Check to see if processor is capable of changing FIDVID */
157 /* otherwise it will throw a GP# when reading FIDVID_STATUS */
158 cpuid1 = cpuid(0x80000007);
159 if( (cpuid1.edx & 0x6) == 0x6 ) {
161 /* Read FIDVID_STATUS */
162 msr=rdmsr(0xc0010042);
163 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
166 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
167 init_fidvid_bsp(bsp_apicid);
169 /* show final fid and vid */
170 msr=rdmsr(0xc0010042);
171 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
174 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
177 needs_reset = optimize_link_coherent_ht();
178 needs_reset |= optimize_link_incoherent_ht(sysinfo);
180 printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
184 print_info("ht reset -\r\n");
188 allow_all_aps_stop(bsp_apicid);
190 /* It's the time to set ctrl now; */
191 printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
192 sysinfo->nodes, sysinfo->ctrl, spd_addr);
193 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
194 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
196 rs690_before_pci_init();
197 sb600_before_pci_init();