2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #define RAMINIT_SYSINFO 1
24 #define K8_SET_FIDVID 1
25 #define QRANK_DIMM_SUPPORT 1
26 #if CONFIG_LOGICAL_CPUS==1
27 #define SET_NB_CFG_54 1
36 #define ICS951462_ADDRESS 0x69
37 #define SMBUS_HUB 0x71
40 #include <device/pci_def.h>
42 #include <device/pnp_def.h>
43 #include <arch/romcc_io.h>
44 #include <cpu/x86/lapic.h>
45 #include "option_table.h"
46 #include "pc80/mc146818rtc_early.c"
47 #include "pc80/serial.c"
48 #include "arch/i386/lib/console.c"
50 #define post_code(x) outb(x, 0x80)
52 #include <cpu/amd/model_fxx_rev.h>
53 #include "northbridge/amd/amdk8/raminit.h"
54 #include "cpu/amd/model_fxx/apic_timer.c"
55 #include "lib/delay.c"
57 #if CONFIG_USE_INIT == 0
58 #include "lib/memcpy.c"
61 #include "cpu/x86/lapic/boot_cpu.c"
62 #include "northbridge/amd/amdk8/reset_test.c"
63 #include "northbridge/amd/amdk8/debug.c"
64 #include "superio/ite/it8712f/it8712f_early_serial.c"
66 #include "cpu/amd/mtrr/amd_earlymtrr.c"
67 #include "cpu/x86/bist.h"
69 #include "northbridge/amd/amdk8/setup_resource_map.c"
71 #include "southbridge/amd/rs690/rs690_early_setup.c"
72 #include "southbridge/amd/sb600/sb600_early_setup.c"
74 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
75 static void memreset(int controllers, const struct mem_controller *ctrl)
79 /* called in raminit_f.c */
80 static inline void activate_spd_rom(const struct mem_controller *ctrl)
84 /*called in raminit_f.c */
85 static inline int spd_read_byte(u32 device, u32 address)
87 return smbus_read_byte(device, address);
90 #include "northbridge/amd/amdk8/amdk8.h"
91 #include "northbridge/amd/amdk8/incoherent_ht.c"
92 #include "northbridge/amd/amdk8/raminit.c"
93 #include "northbridge/amd/amdk8/coherent_ht.c"
94 #include "sdram/generic_sdram.c"
95 #include "resourcemap.c"
97 #include "cpu/amd/dualcore/dualcore.c"
99 #include "cpu/amd/car/copy_and_run.c"
100 #include "cpu/amd/car/post_cache_as_ram.c"
102 #include "cpu/amd/model_fxx/init_cpus.c"
104 #include "cpu/amd/model_fxx/fidvid.c"
106 #if USE_FALLBACK_IMAGE == 1
108 #include "northbridge/amd/amdk8/early_ht.c"
110 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
112 /* Is this a cpu only reset? Is this a secondary cpu? */
113 if ((cpu_init_detectedx) || (!boot_cpu())) {
114 if (last_boot_normal()) { /* RTC already inited */
120 /* Nothing special needs to be done to find bus 0 */
121 /* Allow the HT devices to be found */
122 enumerate_ht_chain();
124 /* sb600_lpc_port80(); */
127 /* Is this a deliberate reset by the bios */
128 if (bios_reset_detected() && last_boot_normal()) {
131 /* This is the primary cpu how should I boot? */
132 else if (do_normal_boot()) {
139 __asm__ volatile ("jmp __normal_image": /* outputs */
140 :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
145 #endif /* USE_FALLBACK_IMAGE == 1 */
147 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
149 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
152 #if USE_FALLBACK_IMAGE == 1
153 failover_process(bist, cpu_init_detectedx);
155 real_main(bist, cpu_init_detectedx);
158 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
160 static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
164 struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
168 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
174 /* it8712f_enable_serial does not use its 1st parameter. */
175 it8712f_enable_serial(0, TTYS0_BASE);
179 /* Halt if there was a built in self test failure */
180 report_bist_failure(bist);
181 printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
183 setup_dbm690t_resource_map();
185 setup_coherent_ht_domain();
187 #if CONFIG_LOGICAL_CPUS==1
188 /* It is said that we should start core1 after all core0 launched */
189 wait_all_core0_started();
192 wait_all_aps_started(bsp_apicid);
194 ht_setup_chains_x(sysinfo);
196 /* run _early_setup before soft-reset. */
200 msr=rdmsr(0xc0010042);
201 printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
204 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
205 init_fidvid_bsp(bsp_apicid);
207 /* show final fid and vid */
208 msr=rdmsr(0xc0010042);
209 printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
211 needs_reset = optimize_link_coherent_ht();
212 needs_reset |= optimize_link_incoherent_ht(sysinfo);
213 printk_debug("needs_reset=0x%x\n", needs_reset);
217 print_info("ht reset -\r\n");
221 allow_all_aps_stop(bsp_apicid);
223 /* It's the time to set ctrl now; */
224 printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
225 sysinfo->nodes, sysinfo->ctrl, spd_addr);
226 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
227 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
229 rs690_before_pci_init();
230 sb600_before_pci_init();