2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 uses USE_FALLBACK_IMAGE
26 uses HAVE_FALLBACK_BOOT
29 uses HAVE_OPTION_TABLE
31 uses CONFIG_MAX_PHYSICAL_CPUS
32 uses CONFIG_LOGICAL_CPUS
40 uses ROM_SECTION_OFFSET
41 uses CONFIG_ROM_PAYLOAD
42 uses CONFIG_ROM_PAYLOAD_START
43 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
51 uses LB_CKS_RANGE_START
54 uses MAINBOARD_PART_NUMBER
57 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
58 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
59 uses COREBOOT_EXTRA_VERSION
64 uses DEFAULT_CONSOLE_LOGLEVEL
65 uses MAXIMUM_CONSOLE_LOGLEVEL
66 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
67 uses CONFIG_CONSOLE_SERIAL8250
76 uses CONFIG_CONSOLE_VGA
77 uses CONFIG_PCI_ROM_RUN
78 uses HW_MEM_HOLE_SIZEK
79 uses HT_CHAIN_UNITID_BASE
80 uses HT_CHAIN_END_UNITID_BASE
81 uses SB_HT_CHAIN_ON_BUS0
86 uses DCACHE_RAM_GLOBAL_VAR_SIZE
89 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
90 uses CONFIG_USE_PRINTK_IN_CAR
100 ## ROM_SIZE is the size of boot ROM that this board will use.
102 default ROM_SIZE=524288
105 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
107 #default FALLBACK_SIZE=131072
109 default FALLBACK_SIZE=0x40000
112 ## Build code for the fallback boot
114 default HAVE_FALLBACK_BOOT=1
117 ## Build code to reset the motherboard from coreboot
119 default HAVE_HARD_RESET=1
122 ## Build code to export a programmable irq routing table
124 default HAVE_PIRQ_TABLE=1
125 default IRQ_SLOT_COUNT=11
128 ## Build code to export an x86 MP table
129 ## Useful for specifying IRQ routing values
131 default HAVE_MP_TABLE=1
134 ## Build code to export a CMOS option table
136 default HAVE_OPTION_TABLE=0
139 ## Move the default coreboot cmos range off of AMD RTC registers
141 default LB_CKS_RANGE_START=49
142 default LB_CKS_RANGE_END=122
143 default LB_CKS_LOC=123
146 ## Build code for SMP support
147 ## Only worry about 2 micro processors
150 default CONFIG_MAX_CPUS=2
152 default CONFIG_MAX_PHYSICAL_CPUS=1
153 default CONFIG_LOGICAL_CPUS=1
156 default CONFIG_CHIP_NAME=1
159 default HW_MEM_HOLE_SIZEK=0x100000
162 default CONFIG_CONSOLE_VGA=1
163 default CONFIG_PCI_ROM_RUN=1
165 # BTDC: Only one HT device on Herring.
167 #default HT_CHAIN_UNITID_BASE=0x6
168 default HT_CHAIN_UNITID_BASE=0x0
172 default HT_CHAIN_END_UNITID_BASE=0x1
174 #make the SB HT chain on bus 0
175 default SB_HT_CHAIN_ON_BUS0=1
178 ## enable CACHE_AS_RAM specifics
180 default USE_DCACHE_RAM=1
181 default DCACHE_RAM_BASE=0xc8000
182 default DCACHE_RAM_SIZE=0x8000
183 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
184 default CONFIG_USE_INIT=0
187 ## Build code to setup a generic IOAPIC
189 default CONFIG_IOAPIC=1
192 ## Clean up the motherboard id strings
194 default MAINBOARD_PART_NUMBER="dbm690t"
195 default MAINBOARD_VENDOR="amd"
196 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
197 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
201 ### coreboot layout values
204 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
205 default ROM_IMAGE_SIZE = 65536
208 ## Use a small 8K stack
210 default STACK_SIZE=0x2000
213 ## Use a small 16K heap
215 default HEAP_SIZE=0x4000
218 ## Only use the option table in a normal image
220 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
221 default USE_OPTION_TABLE = 0
224 ## coreboot C code runs at this location in RAM
226 default _RAMBASE=0x00004000
229 ## Load the payload from the ROM
231 default CONFIG_ROM_PAYLOAD = 1
234 ### Defaults of options that you may want to override in the target config file
238 ## The default compiler
240 default CC="$(CROSS_COMPILE)gcc -m32"
244 ## Disable the gdb stub by default
246 default CONFIG_GDB_STUB=0
249 default CONFIG_USE_PRINTK_IN_CAR=1
252 ## The Serial Console
255 # To Enable the Serial Console
256 default CONFIG_CONSOLE_SERIAL8250=1
258 ## Select the serial console baud rate
259 default TTYS0_BAUD=115200
260 #default TTYS0_BAUD=57600
261 #default TTYS0_BAUD=38400
262 #default TTYS0_BAUD=19200
263 #default TTYS0_BAUD=9600
264 #default TTYS0_BAUD=4800
265 #default TTYS0_BAUD=2400
266 #default TTYS0_BAUD=1200
268 # Select the serial console base port
269 default TTYS0_BASE=0x3f8
271 # Select the serial protocol
272 # This defaults to 8 data bits, 1 stop bit, and no parity
273 default TTYS0_LCS=0x3
276 ### Select the coreboot loglevel
278 ## EMERG 1 system is unusable
279 ## ALERT 2 action must be taken immediately
280 ## CRIT 3 critical conditions
281 ## ERR 4 error conditions
282 ## WARNING 5 warning conditions
283 ## NOTICE 6 normal but significant condition
284 ## INFO 7 informational
285 ## DEBUG 8 debug-level messages
286 ## SPEW 9 Way too many details
288 ## Request this level of debugging output
289 default DEFAULT_CONSOLE_LOGLEVEL=8
290 ## At a maximum only compile in this level of debugging
291 default MAXIMUM_CONSOLE_LOGLEVEL=8
294 ## Select power on after power fail setting
295 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
297 default CONFIG_VIDEO_MB=1
298 default CONFIG_GFXUMA=1