src/mainboard/amd/dbm690t/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15 ## You should have received a copy of the GNU General Public License
  16 ## along with this program; if not, write to the Free Software
  17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 ##
  19 ##
  20 ##
  21
  22
  23 ##
  24 ## Compute the location and size of where this firmware image
  25 ## (coreboot plus bootloader) will live in the boot rom chip.
  26 ##
  27 if USE_FALLBACK_IMAGE
  28         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  29         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
  30 else
  31         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  32         default ROM_SECTION_OFFSET = 0
  33 end
  34
  35 ##
  36 ## Compute the start location and size size of
  37 ## The coreboot bootloader.
  38 ##
  39 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  40 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  41
  42 ##
  43 ## Compute where this copy of coreboot will start in the boot rom
  44 ##
  45 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  46
  47 ##
  48 ## Compute a range of ROM that can cached to speed up coreboot,
  49 ## execution speed.
  50 ##
  51 ## XIP_ROM_SIZE must be a power of 2.
  52 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  53 ##
  54 default XIP_ROM_SIZE=65536
  55 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  56
  57 arch i386 end
  58
  59 ##
  60 ## Build the objects we have code for in this directory.
  61 ##
  62
  63 driver mainboard.o
  64
  65 #dir /drivers/si/3114
  66
  67 if HAVE_MP_TABLE object mptable.o end
  68 if HAVE_PIRQ_TABLE
  69         object get_bus_conf.o
  70         object irq_tables.o
  71 end
  72
  73 if HAVE_ACPI_TABLES
  74         object acpi_tables.o
  75         object fadt.o
  76         makerule dsdt.c
  77                 depends "$(MAINBOARD)/acpi/*.asl"
  78                 action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
  79                 action  "mv dsdt.hex dsdt.c"
  80         end
  81         object ./dsdt.o
  82 end
  83
  84 #object reset.o
  85
  86 if USE_DCACHE_RAM
  87
  88         if CONFIG_USE_INIT
  89
  90                 makerule ./cache_as_ram_auto.o
  91                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  92                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  93                 end
  94
  95         else
  96
  97                 makerule ./cache_as_ram_auto.inc
  98                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  99                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
 100                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 101                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 102                 end
 103
 104         end
 105
 106 end
 107 ##
 108 ## Build our 16 bit and 32 bit coreboot entry code
 109 ##
 110 mainboardinit cpu/x86/16bit/entry16.inc
 111 mainboardinit cpu/x86/32bit/entry32.inc
 112 ldscript /cpu/x86/16bit/entry16.lds
 113 if USE_DCACHE_RAM
 114         if CONFIG_USE_INIT
 115                 ldscript /cpu/x86/32bit/entry32.lds
 116         end
 117
 118         if CONFIG_USE_INIT
 119                 ldscript      /cpu/amd/car/cache_as_ram.lds
 120         end
 121 end
 122
 123 ##
 124 ## Build our reset vector (This is where coreboot is entered)
 125 ##
 126 if USE_FALLBACK_IMAGE
 127         mainboardinit cpu/x86/16bit/reset16.inc
 128         ldscript /cpu/x86/16bit/reset16.lds
 129 else
 130         mainboardinit cpu/x86/32bit/reset32.inc
 131         ldscript /cpu/x86/32bit/reset32.lds
 132 end
 133
 134 ##
 135 ## Include an id string (For safe flashing)
 136 ##
 137 mainboardinit arch/i386/lib/id.inc
 138 ldscript /arch/i386/lib/id.lds
 139
 140 if USE_DCACHE_RAM
 141         ##
 142         ## Setup Cache-As-Ram
 143         ##
 144         mainboardinit cpu/amd/car/cache_as_ram.inc
 145 end
 146
 147 ###
 148 ### This is the early phase of coreboot startup
 149 ### Things are delicate and we test to see if we should
 150 ### failover to another image.
 151 ###
 152 if USE_FALLBACK_IMAGE
 153         if USE_DCACHE_RAM
 154                 ldscript /arch/i386/lib/failover.lds
 155         else
 156                 ldscript /arch/i386/lib/failover.lds
 157                 mainboardinit ./failover.inc
 158         end
 159 end
 160
 161 ###
 162 ### O.k. We aren't just an intermediary anymore!
 163 ###
 164
 165 ##
 166 ## Setup RAM
 167 ##
 168 if USE_DCACHE_RAM
 169
 170         if CONFIG_USE_INIT
 171                 initobject cache_as_ram_auto.o
 172         else
 173                 mainboardinit ./cache_as_ram_auto.inc
 174         end
 175
 176 end
 177
 178 ##
 179 ## Include the secondary Configuration files
 180 ##
 181 if CONFIG_CHIP_NAME
 182         config chip.h
 183 end
 184
 185 #The variables belong to mainboard are defined here.
 186
 187 #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
 188 #Define vga_rom_address = 0xfff0000
 189 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 190 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 191 #                                          1: the system allows a PCIE link to be established on Dev2 or Dev3.
 192 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 193 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 194 #Define gfx_tmds, 0: didn't support TMDS, 1: support
 195 #Define gfx_compliance, 0: didn't support compliance, 1: support
 196 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
 197 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 198 chip northbridge/amd/amdk8/root_complex
 199         device apic_cluster 0 on
 200                 chip cpu/amd/socket_S1G1
 201                 device apic 0 on end
 202                 end
 203         end
 204         device pci_domain 0 on
 205                 chip northbridge/amd/amdk8
 206                         device pci 18.0 on #  southbridge
 207                                 chip southbridge/amd/rs690
 208                                         device pci 0.0 on end # HT      0x7910
 209                                         device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 210                                                 chip drivers/pci/onboard
 211                                                         device pci 5.0 on end   # Internal Graphics 0x791F
 212                                                         register "rom_address" = "0xfff00000"
 213                                                 end
 214                                         end
 215                                         device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 216                                         device pci 3.0 off end # PCIE P2P bridge        0x791b
 217                                         device pci 4.0 on end # PCIE P2P bridge 0x1914
 218                                         device pci 5.0 on end # PCIE P2P bridge 0x7915
 219                                         device pci 6.0 on end # PCIE P2P bridge 0x7916
 220                                         device pci 7.0 on end # PCIE P2P bridge 0x7917
 221                                         device pci 8.0 off end # NB/SB Link P2P bridge
 222                                         register "vga_rom_address" = "0xfff00000"
 223                                         register "gpp_configuration" = "4"
 224                                         register "port_enable" = "0xfc"
 225                                         register "gfx_dev2_dev3" = "1"
 226                                         register "gfx_dual_slot" = "0"
 227                                         register "gfx_lane_reversal" = "0"
 228                                         register "gfx_tmds" = "0"
 229                                         register "gfx_compliance" = "0"
 230                                         register "gfx_reconfiguration" = "1"
 231                                         register "gfx_link_width" = "0"
 232                                 end
 233                                 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 234                                         device pci 12.0 on end # SATA  0x4380
 235                                         device pci 13.0 on end # USB   0x4387
 236                                         device pci 13.1 on end # USB   0x4388
 237                                         device pci 13.2 on end # USB   0x4389
 238                                         device pci 13.3 on end # USB   0x438a
 239                                         device pci 13.4 on end # USB   0x438b
 240                                         device pci 13.5 on end # USB 2 0x4386
 241                                         device pci 14.0 on # SM        0x4385
 242                                                 chip drivers/generic/generic #dimm 0-0-0
 243                                                         device i2c 50 on end
 244                                                 end
 245                                                 chip drivers/generic/generic #dimm 0-0-1
 246                                                         device i2c 51 on end
 247                                                 end
 248                                                 chip drivers/generic/generic #dimm 0-1-0
 249                                                         device i2c 52 on end
 250                                                 end
 251                                                 chip drivers/generic/generic #dimm 0-1-1
 252                                                         device i2c 53 on end
 253                                                 end
 254                                         end # SM
 255                                         device pci 14.1 on end # IDE    0x438c
 256                                         device pci 14.2 on end # HDA    0x4383
 257                                         device pci 14.3 on # LPC        0x438d
 258                                                 chip superio/ite/it8712f
 259                                                         device pnp 2e.0 off #  Floppy
 260                                                                 io 0x60 = 0x3f0
 261                                                                 irq 0x70 = 6
 262                                                                 drq 0x74 = 2
 263                                                         end
 264                                                         device pnp 2e.1 on #  Com1
 265                                                                 io 0x60 = 0x3f8
 266                                                                 irq 0x70 = 4
 267                                                         end
 268                                                         device pnp 2e.2 off #  Com2
 269                                                                 io 0x60 = 0x2f8
 270                                                                 irq 0x70 = 3
 271                                                         end
 272                                                         device pnp 2e.3 off #  Parallel Port
 273                                                                 io 0x60 = 0x378
 274                                                                 irq 0x70 = 7
 275                                                         end
 276                                                         device pnp 2e.4 off end #  EC
 277                                                         device pnp 2e.5 on #  Keyboard
 278                                                                 io 0x60 = 0x60
 279                                                                 io 0x62 = 0x64
 280                                                                 irq 0x70 = 1
 281                                                         end
 282                                                         device pnp 2e.6 on #  Mouse
 283                                                                 irq 0x70 = 12
 284                                                         end
 285                                                         device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
 286                                                         end
 287                                                         device pnp 2e.8 off #  MIDI
 288                                                                 io 0x60 = 0x300
 289                                                                 irq 0x70 = 9
 290                                                         end
 291                                                         device pnp 2e.9 off #  GAME
 292                                                                 io 0x60 = 0x220
 293                                                         end
 294                                                         device pnp 2e.a off end #  CIR
 295                                                 end     #superio/ite/it8712f
 296                                         end             #LPC
 297                                         device pci 14.4 on end # PCI 0x4384
 298                                         device pci 14.5 on end # ACI 0x4382
 299                                         device pci 14.6 on end # MCI 0x438e
 300                                         register "ide0_enable" = "1"
 301                                         register "sata0_enable" = "1"
 302                                         register "hda_viddid" = "0x10ec0882"
 303                                 end     #southbridge/amd/sb600
 304                         end #  device pci 18.0
 305
 306                         device pci 18.0 on end
 307                         device pci 18.0 on end
 308                         device pci 18.1 on end
 309                         device pci 18.2 on end
 310                         device pci 18.3 on end
 311                 end             #northbridge/amd/amdk8
 312         end #pci_domain
 313 end             #northbridge/amd/amdk8/root_complex
 314