src/mainboard/amd/dbm690t/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15 ## You should have received a copy of the GNU General Public License
  16 ## along with this program; if not, write to the Free Software
  17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 ##
  19 ##
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/nofailovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33
  34 #dir /drivers/si/3114
  35
  36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  37 if CONFIG_GENERATE_PIRQ_TABLE
  38         object get_bus_conf.o
  39         object irq_tables.o
  40 end
  41
  42 if CONFIG_GENERATE_ACPI_TABLES
  43         object acpi_tables.o
  44         object fadt.o
  45         makerule dsdt.c
  46                 depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
  47                 action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
  48                 action  "mv dsdt.hex dsdt.c"
  49         end
  50         object ./dsdt.o
  51 end
  52
  53 #object reset.o
  54
  55         if CONFIG_USE_INIT
  56
  57                 makerule ./cache_as_ram_auto.o
  58                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  59                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  60                 end
  61
  62         else
  63
  64                 makerule ./cache_as_ram_auto.inc
  65                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  66                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  67                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  68                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  69                 end
  70
  71         end
  72
  73 ##
  74 ## Build our 16 bit and 32 bit coreboot entry code
  75 ##
  76 mainboardinit cpu/x86/16bit/entry16.inc
  77 mainboardinit cpu/x86/32bit/entry32.inc
  78 ldscript /cpu/x86/16bit/entry16.lds
  79         if CONFIG_USE_INIT
  80                 ldscript /cpu/x86/32bit/entry32.lds
  81         end
  82
  83         if CONFIG_USE_INIT
  84                 ldscript      /cpu/amd/car/cache_as_ram.lds
  85         end
  86
  87 ##
  88 ## Build our reset vector (This is where coreboot is entered)
  89 ##
  90 if CONFIG_USE_FALLBACK_IMAGE
  91         mainboardinit cpu/x86/16bit/reset16.inc
  92         ldscript /cpu/x86/16bit/reset16.lds
  93 else
  94         mainboardinit cpu/x86/32bit/reset32.inc
  95         ldscript /cpu/x86/32bit/reset32.lds
  96 end
  97
  98 ##
  99 ## Include an id string (For safe flashing)
 100 ##
 101 mainboardinit arch/i386/lib/id.inc
 102 ldscript /arch/i386/lib/id.lds
 103
 104         ##
 105         ## Setup Cache-As-Ram
 106         ##
 107         mainboardinit cpu/amd/car/cache_as_ram.inc
 108
 109 ###
 110 ### This is the early phase of coreboot startup
 111 ### Things are delicate and we test to see if we should
 112 ### failover to another image.
 113 ###
 114 if CONFIG_USE_FALLBACK_IMAGE
 115                 ldscript /arch/i386/lib/failover.lds
 116 end
 117
 118 ###
 119 ### O.k. We aren't just an intermediary anymore!
 120 ###
 121
 122 ##
 123 ## Setup RAM
 124 ##
 125         if CONFIG_USE_INIT
 126                 initobject cache_as_ram_auto.o
 127         else
 128                 mainboardinit ./cache_as_ram_auto.inc
 129         end
 130
 131 ##
 132 ## Include the secondary Configuration files
 133 ##
 134 config chip.h
 135
 136 #The variables belong to mainboard are defined here.
 137
 138 #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
 139 #Define vga_rom_address = 0xfff0000
 140 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 141 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 142 #                                          1: the system allows a PCIE link to be established on Dev2 or Dev3.
 143 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 144 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 145 #Define gfx_tmds, 0: didn't support TMDS, 1: support
 146 #Define gfx_compliance, 0: didn't support compliance, 1: support
 147 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
 148 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 149 chip northbridge/amd/amdk8/root_complex
 150         device apic_cluster 0 on
 151                 chip cpu/amd/socket_S1G1
 152                 device apic 0 on end
 153                 end
 154         end
 155         device pci_domain 0 on
 156                 chip northbridge/amd/amdk8
 157                         device pci 18.0 on #  southbridge
 158                                 chip southbridge/amd/rs690
 159                                         device pci 0.0 on end # HT      0x7910
 160                                         device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 161                                                 chip drivers/pci/onboard
 162                                                         device pci 5.0 on end   # Internal Graphics 0x791F
 163                                                         register "rom_address" = "0xfff00000"
 164                                                 end
 165                                         end
 166                                         device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 167                                         device pci 3.0 off end # PCIE P2P bridge        0x791b
 168                                         device pci 4.0 on end # PCIE P2P bridge 0x7914
 169                                         device pci 5.0 on end # PCIE P2P bridge 0x7915
 170                                         device pci 6.0 on end # PCIE P2P bridge 0x7916
 171                                         device pci 7.0 on end # PCIE P2P bridge 0x7917
 172                                         device pci 8.0 off end # NB/SB Link P2P bridge
 173                                         register "vga_rom_address" = "0xfff00000"
 174                                         register "gpp_configuration" = "4"
 175                                         register "port_enable" = "0xfc"
 176                                         register "gfx_dev2_dev3" = "1"
 177                                         register "gfx_dual_slot" = "0"
 178                                         register "gfx_lane_reversal" = "0"
 179                                         register "gfx_tmds" = "0"
 180                                         register "gfx_compliance" = "0"
 181                                         register "gfx_reconfiguration" = "1"
 182                                         register "gfx_link_width" = "0"
 183                                 end
 184                                 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 185                                         device pci 12.0 on end # SATA  0x4380
 186                                         device pci 13.0 on end # USB   0x4387
 187                                         device pci 13.1 on end # USB   0x4388
 188                                         device pci 13.2 on end # USB   0x4389
 189                                         device pci 13.3 on end # USB   0x438a
 190                                         device pci 13.4 on end # USB   0x438b
 191                                         device pci 13.5 on end # USB 2 0x4386
 192                                         device pci 14.0 on # SM        0x4385
 193                                                 chip drivers/generic/generic #dimm 0-0-0
 194                                                         device i2c 50 on end
 195                                                 end
 196                                                 chip drivers/generic/generic #dimm 0-0-1
 197                                                         device i2c 51 on end
 198                                                 end
 199                                                 chip drivers/generic/generic #dimm 0-1-0
 200                                                         device i2c 52 on end
 201                                                 end
 202                                                 chip drivers/generic/generic #dimm 0-1-1
 203                                                         device i2c 53 on end
 204                                                 end
 205                                         end # SM
 206                                         device pci 14.1 on end # IDE    0x438c
 207                                         device pci 14.2 on end # HDA    0x4383
 208                                         device pci 14.3 on # LPC        0x438d
 209                                                 chip superio/ite/it8712f
 210                                                         device pnp 2e.0 off #  Floppy
 211                                                                 io 0x60 = 0x3f0
 212                                                                 irq 0x70 = 6
 213                                                                 drq 0x74 = 2
 214                                                         end
 215                                                         device pnp 2e.1 on #  Com1
 216                                                                 io 0x60 = 0x3f8
 217                                                                 irq 0x70 = 4
 218                                                         end
 219                                                         device pnp 2e.2 off #  Com2
 220                                                                 io 0x60 = 0x2f8
 221                                                                 irq 0x70 = 3
 222                                                         end
 223                                                         device pnp 2e.3 off #  Parallel Port
 224                                                                 io 0x60 = 0x378
 225                                                                 irq 0x70 = 7
 226                                                         end
 227                                                         device pnp 2e.4 off end #  EC
 228                                                         device pnp 2e.5 on #  Keyboard
 229                                                                 io 0x60 = 0x60
 230                                                                 io 0x62 = 0x64
 231                                                                 irq 0x70 = 1
 232                                                         end
 233                                                         device pnp 2e.6 on #  Mouse
 234                                                                 irq 0x70 = 12
 235                                                         end
 236                                                         device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
 237                                                         end
 238                                                         device pnp 2e.8 off #  MIDI
 239                                                                 io 0x60 = 0x300
 240                                                                 irq 0x70 = 9
 241                                                         end
 242                                                         device pnp 2e.9 off #  GAME
 243                                                                 io 0x60 = 0x220
 244                                                         end
 245                                                         device pnp 2e.a off end #  CIR
 246                                                 end     #superio/ite/it8712f
 247                                         end             #LPC
 248                                         device pci 14.4 on end # PCI 0x4384
 249                                         device pci 14.5 on end # ACI 0x4382
 250                                         device pci 14.6 on end # MCI 0x438e
 251                                         register "ide0_enable" = "1"
 252                                         register "sata0_enable" = "1"
 253                                         register "hda_viddid" = "0x10ec0882"
 254                                 end     #southbridge/amd/sb600
 255                         end #  device pci 18.0
 256
 257                         device pci 18.0 on end
 258                         device pci 18.0 on end
 259                         device pci 18.1 on end
 260                         device pci 18.2 on end
 261                         device pci 18.3 on end
 262                 end             #northbridge/amd/amdk8
 263         end #pci_domain
 264 end             #northbridge/amd/amdk8/root_complex
 265