2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
27 #include <console/console.h>
28 #include "cpu/x86/bist.h"
29 #include "cpu/x86/msr.h"
30 #include <cpu/amd/lxdef.h>
31 #include "southbridge/amd/cs5536/cs5536.h"
33 #include "southbridge/amd/cs5536/early_smbus.c"
34 #include "southbridge/amd/cs5536/early_setup.c"
35 #include "superio/winbond/w83627hf/early_serial.c"
37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
39 static inline int spd_read_byte(unsigned int device, unsigned int address)
41 return smbus_read_byte(device, address);
44 #define ManualConf 0 /* Do automatic strapped PLL config */
45 #define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
46 #define PLLMSRlo 0x00DE60EE
48 #include "northbridge/amd/lx/raminit.h"
49 #include "northbridge/amd/lx/pll_reset.c"
50 #include "northbridge/amd/lx/raminit.c"
51 #include "lib/generic_sdram.c"
52 #include "cpu/amd/geode_lx/cpureginit.c"
53 #include "cpu/amd/geode_lx/syspreinit.c"
54 #include "cpu/amd/geode_lx/msrinit.c"
56 void main(unsigned long bist)
59 static const struct mem_controller memctrl[] = {
60 {.channel0 = {DIMM0, DIMM1}}
68 /* Note: must do this AFTER the early_setup! It is counting on some
69 * early MSR setup for CS5536.
71 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
74 /* Halt if there was a built in self test failure */
75 report_bist_failure(bist);
77 pll_reset(ManualConf);
79 cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
81 sdram_initialize(1, memctrl);
83 /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */